參數(shù)資料
型號(hào)： AD995PCBZ
廠商： Analog Devices, Inc.
英文描述： 1 GSPS Quadrature Digital Upconverter w/18-Bit IQ Data Path and 14-Bit DAC
中文描述： 1 GSPS的正交數(shù)字上變頻器w/18-Bit智商數(shù)據(jù)路徑和14位DAC
文件頁(yè)數(shù)： 19/38頁(yè)
文件大?。?/td> 602K
代理商： AD995PCBZ
PRELIMINARY TECHNICAL DATA
AD9957
Rev. PrF | Page 19 of 38
REFCLK INPUT
The AD9957 supports a few methods for generating the internal
system clock. An on-chip oscillator circuit is available for initi-
ating a low frequency reference signal by connecting a crystal to
the clock input pins. The system clock may also be generated
using the internal, PLL-based reference clock multiplier, allow-
ing the part to operate with a low frequency clock source while
still providing a high update rate for the DDS and DAC. Using
the clock multiplier can impact the output phase noise charac-
teristics - for best phase noise performance, a clean, stable clock
with a high slew is required. A clock of frequency higher than
the maximum allowable clock rate can be used if the REFCLK
input divide by 2 is enabled using the REFCLK input divider
enable bit CFR3<15>.
REFCLK PLL
Enabling the PLL (via the PLL Enable Bit, CFR3<8>) allows
multiplication of the reference clock frequency. The multiplica-
tion factor in the clock multiplier is set by bits CFR3 <7:1> with
values ranging from 8 to 10 and 12 to 127 (decimal). Pro-
gramming CFR3<7:1> for values less than 8 or 11 is not valid
and will cause unpredictable device performance. The system
clock rate with the clock multiplier enabled is equal to the refer-
ence clock rate times the multiplication factor. When using the
clock multiplier, the correct VCO and charge pump current
must be selected. The VCO range is selected by programming
the VCO SEL bits, CFR3 <26:24>.. The charge pump current is
programmed through the ICP bits, CFR3<21:19>. See the regis-
ter map for Tables showing the available settings
Whenever the PLL clock multiplier is enabled or the multiplica-
tion value changed, the PLL must reacquire lock. Once lock is
achieved, the LOCK_DETECT signal will be output on pin 19.
While the PLL is out of lock, transmission in the QDUC is
gated off.
REFCLK PLL WITH CRYSTAL
The on-chip oscillator for crystal operation is enabled using
XTAL_SEL (pin 95). The XTAL_SEL pin is an analog input,
operating on 1.8V logic. With the on-chip oscillator enabled,
connecting an external crystal across the REF_CLK and
REF_CLKB inputs produces a low frequency reference clock.
The range of frequencies supported is listed in the specification
table.
A buffer outputs a regenerated REFCLK/crystal oscillator signal
on the XTAL_OUT pin (pin 94). Harmonic interference effects
may be mitigated using DRV slew rate control bits
CFR3<31:30>.
Table 5 summarizes the clock mode options. See the Register
Table/Map section for more detail.
XTAL_SEL
Pin (95)
High = 1.8 V logic
CFR1<7:1> PLL, Bits = M
12 ≤ M ≤ 127, or
8 ≤ M ≤ 10
M < 8, M=11, or
M > 127
12 ≤ M ≤ 127 or
8 ≤ M ≤ 10
M < 8, M=11, or
M > 127
PLL Enabled (CFR3<15>
Yes CFR3<15>=1
System Clock
(f
SYS CLK
)
f
SYS CLK
= f
OSC
× M
Min/Max Freq. Range (MHz)
500 < f
SYSCLK
< 1000
High = 1.8 V logic
No
f
SYS CLK
= F
OSC
20 < f
SYSCLK
< 30
Low
Yes CFR3<15> = 1
f
SYS CLK
= F
REF CLK
× M
500 < f
SYSCLK
< 1000
Low
No
f
SYS CLK
= F
REF CLK
0 < f
SYS CLK
< 1000
Table 5 Clock Mode Options
REFCLK: EXTERNAL INTERFACE
The reference clock input circuitry has two modes of operation.
The first mode configures it as an input buffer. In this mode, the
reference clock must be ac-coupled to the input due to internal
dc biasing. This mode supports either differential or single-
ended configurations. If single-ended mode is desired, CLKB
(Pin 91) should be decoupled to AVDD or AGND via a 0.1 μF
capacitor. The next three figures exemplify common reference
clock configurations for the AD9957.
Figure 14
The reference clock inputs can also support an LVPECL or
PECL driver as the reference clock source.
1:1
BALUN
CLK
PIN 90
REFERENCE
CLOCK
SOURCE
CLK
PIN 91
50
Ω
0.1
μ
F
0.1
μ
F
05252-032
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