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參數(shù)資料
| 型號： | AD995PCBZ |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 1 GSPS Quadrature Digital Upconverter w/18-Bit IQ Data Path and 14-Bit DAC |
| 中文描述： | 1 GSPS的正交數(shù)字上變頻器w/18-Bit智商數(shù)據(jù)路徑和14位DAC |
| 文件頁數(shù)： | 36/38頁 |
| 文件大?。?/td> | 602K |
| 代理商： | AD995PCBZ |
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AD9957
PRELIMINARY TECHNICAL DATA
Rev. PrF | Page 36 of 38
ble 4). If the PLL is enabled (CFR3<8>), a valid value must
be programmed here for proper PLL operation. If the PLL
is disabled, these bits are ignored.
CFR3<0>
:
REFCLK input doubler active bit
When
CFR3<0>
= 0
(default)
the reference clock is fed di-
rectly to the PFD.
When
CFR3<0>
= 1, the reference clock is doubled in fre-
quency prior to being fed to the PFD.
Auxilliary DAC Control Register
These 8 bits control the auxiliary DAC that modulates the full
scale current of the Tx DAC. For a default DAC_Rset value of
10K, these bits modulate the DAC output full scale current be-
tween 8.66mA and 31.66mA, with each LSB representing ap-
proximately 90μA of resolution.
IO Update Rate Register
This register sets the interval for the down counter which di-
vides the system clock down to an internal I/O update interval
period. When the internal I/O Update mode is disabled, this
register is ignored. Each LSB represents one SYNC_CLK cycle,
so the interval for an internal I/O update rate varies between 1
and 2^32( 4,294,967,296) sync_clock cycles, where a sync_clock
cycle is of a system clock cycle.
QDUC RAM Segment Registers (QRSR0, QRSR1)
These registers program the behavior of the internal RAM con-
troller for when the RAM is configured to drive QDUC data or
drive the input scalars. QRSR0 feeds data to the I-channel and
QRSR1 feeds data to the Q-channel. These registers serve no
function when the AD9957 is programmed to be in single-tone
mode.
QRSRX<47:32> RAM Segment Address Ramp Rate
This 16 bit word controls the period between QDUC
RAM segment steps. Each LSB in this word weights
the delay by 1 SYNC_CLK cycle (which is the sys-
tem clock rate).
QRSRX<31:22> RAM Segment Final Address
This 10 bit word specifies the final address location in
the RAM where the data profile is stored.
QRSRX<21:16> OPEN
QRSRX<15:6> RAM Segment Beginning Address
This 10 bit word specifies the beginning address loca-
tion in the RAM where the data profile is stored.
QRSRX<5:3> OPEN
QSRX<2:0> RAM Segment Mode Control
This 3 bit word specifies the behavior the RAM con-
troller follows when stepping through the Segment ac-
cording to the following table. Note, the behavior in-
dicated refers to the RAM address itself, not necessar-
ily the data stored and sent to the QDUC.
QSRX<2:0>
RAM Mode
000
Direct Switch (Beginning Address only)
001
Ramp Up
010
Bidirectional Ramp (ramp up, ramp down)
011
Continuous Bidirectional (ramp up, ramp
down, ramp up, etc)
100
Continous recirculate (Ramp up from
beginning to final address, then immediately
return to beginning address and repeat).
101, 110,
111
Not Used
Frequency Tuning Word Register (FTW)
This register sets the frequency tuning word of the DDS core,
which is either the output frequency (single tone mode) or the
carrier frequency (modulator mode). When the
Phase/Frequency/Amplitude Profiles are enabled, this register
serves no function.
Phase Offset Word Register (POW)
This register controls the phase offset of the DDS core in either
the output frequency (single tone mode) or the carrier fre-
quency (modulator mode). When the
Phase/Frequency/Amplitude Profiles are enabled, this register
serves no function.
Amplitude Scale Factor (ASF)
This register controls the digital multiplier (amplitude scale
factor) inside the DDS core itself. It does not affect the digital
multiplier immediately prior to the DAC . In automatic OSK
mode, this controls the ramp rate and final value of the ampli-
tude ramping function. In manual OSK mode, only the Ampli-
tude Scale Factor is used, the Amplitude Ramp Rate is ‘don’t
care’ When the Phase /Frequency /Amplitude Profiles are en-
abled, this register serves no function.
QDUC Profile X Register (QDUC-PXR)/
Single Tone Profile X Register (ST-PXR)
There are 8 special purpose registers which reside at addresses
h’0E to h’15. These registers can take on one of three roles: they
can either be QDUC Profile Registers, RAM Profile Registers or
Single Tone Profile Registers.
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