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參數資料
| 型號： | AD9958BCPZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號調理 |
| 英文描述： | 2-Channel 500 MSPS DDS with 10-Bit DACs |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, QCC56 |
| 封裝： | 8 X 8 MM, LEAD FREE, MO-220-VLLD-2, LFCSP-56 |
| 文件頁數： | 37/40頁 |
| 文件大?。?/td> | 1051K |
| 代理商： | AD9958BCPZ |
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AD9958
The RU/RD bits control the amplitude RU/RD time of a
channel (see the Output Amplitude Control Mode section).
Rev. 0 | Page 37 of 40
FR1 <12:14> profile pin configuration bits.
The profile pin configuration bits control the configuration of
the data and SDIO pins for the different modulation modes. See
the Modulation Mode section for details.
FR1 <15> open.
FR1 <17:16> charge pump current control.
FR1 <17:16> = 00 (default), the charge pump current is 75 μA.
= 01 charge pump current is 100 μA.
= 10 charge pump current is 125 μA.
= 11 charge pump current is 150 μA.
FR1 <22:18> PLL divider values.
FR1 <22:18>, if the value is > 3 and < 21, the PLL is enabled and
the value sets the multiplication factor. If the value is < 4 or >20
the PLL is disabled.
FR1 <23> PLL VCO gain.
FR1 <23> = 0 (default), the low range (system clock below
160 MHz). FR1 <23> = 1, the high range (system clock above
255 MHz).
Function Register 2 (FR2) Description
The FR2 is comprised of two bytes located in Address 0x02.
The FR2 is used to control the various functions, features, and
modes of the AD9958. The functionality of each bit is detailed
as follows:
FR2<1:0> system clock offset.
See the Synchronizing Multiple AD9958 Devices section for
more details.
FR2 <3:2> open.
FR2 <4> multi-device synchronization mask bit.
FR2 <5> multi-device synchronization status bit.
FR2 <6> multi-device synchronization master enable bit.
FR2<7> multi-device synchronization slave enable bit.
FR2 <4:7>. see the Synchronizing Multiple AD9958 Devices
section for more details.
FR2 <11:8> open.
FR2 <12> both channels clear phase accumulator.
FR2 <12> = 0 (default), the phase accumulator functions as
normal. FR2 <12> = 1, the phase accumulator memory
elements for both channels are asynchronously cleared.
FR2 <13> both channels auto clear phase accumulator.
FR2 <13> = 0 (default). A new frequency tuning word is applied
to the inputs of the phase accumulator, but not loaded into the
accumulator.
FR2 <13> = 1. This bit automatically synchronously clears
(loads zeros into) the phase accumulator for one cycle upon
reception of the I/O update sequence indicator on both
channels.
FR2 <14> both channels clear sweep accumulator.
FR2 <14> = 0 (default), the sweep accumulator functions as
normal.FR2 <14> = 1, the sweep accumulator memory
elements for both channels are asynchronously cleared.
FR2 <15> both channels auto clear sweep accumulator.
FR2 <15> = 0 (default). A new delta word is applied to the
input, as in normal operation, but not loaded into the accumu-
lator. FR2 <15> = 1. This bit automatically synchronously clears
(loads 0s) the sweep accumulator for one cycle upon reception
of the I/O_UPDATE sequence indicator on both channels.
CHANNEL FUNCTION REGISTER (CFR)
DESCRIPTION
CFR <0> enable sine output.
CFR <0> = 0 (default). The angle-to-amplitude conversion logic
employs a cosine function. CFR <0> = 1. The angle-to-
amplitude conversion logic employs a sine function.
CFR <1> clear phase accumulator.
CFR <1> = 0 (default). The phase accumulator functions as
normal. CFR <1> = 1. The phase accumulator memory
elements are asynchronously cleared.
CFR <2> clear phase accumulator.
CFR <2> = 0 (default). A new frequency tuning word is applied
to the inputs of the phase accumulator, but not loaded into the
accumulator. CFR <2> = 1. This bit automatically synchro-
nously clears (loads 0s) the phase accumulator for one cycle
upon reception of the I/O_UPDATE sequence indicator.
CFR <3> clear frequency accumulator.
CFR <3> = 0 (default). The sweep accumulator functions as
normal .CFR <3> = 1. The sweep accumulator memory
elements are asynchronously cleared.
CFR <4> auto clear sweep accumulator.
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相關代理商/技術參數 |
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| AD9958BCPZ-REEL7 | 功能描述:IC DDS DUAL 10BIT DAC 56LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數字合成 (DDS) 系列:- 產品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9959 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4 Channel 500MSPS DDS with 10-bit DACs |
| AD9959/PCBZ | 功能描述:BOARD EVALUATION FOR AD9959 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| AD9959/PCBZ | 制造商:Analog Devices 功能描述:AD9959, DDS, DAC, GUI, USB, EVALUATION B |
| AD9959/PCBZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, 500 MSPS DDS with 10-Bit DACs |
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