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參數(shù)資料
| 型號(hào)： | AD9958BCPZ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 模擬信號(hào)調(diào)理 |
| 英文描述： | 2-Channel 500 MSPS DDS with 10-Bit DACs |
| 中文描述： | SPECIALTY ANALOG CIRCUIT, QCC56 |
| 封裝： | 8 X 8 MM, LEAD FREE, MO-220-VLLD-2, LFCSP-56 |
| 文件頁數(shù)： | 24/40頁 |
| 文件大小： | 1051K |
| 代理商： | AD9958BCPZ |
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AD9958
Method two is by setting the CFR <14> bit and issuing an I/O
update. If sweep is enabled and CFR <14> is set, the ramp rate
timer loads the value determined by the profile pin: If the
profile pin is high the ramp rate timer loads the RSRR, if the
profile pin is low the ramp rate timer loads the FSRR.
Rev. 0 | Page 24 of 40
Frequency Linear Sweep Example: AFP Bits = 10
Modulation level bits = 00, sweep enable = 1, no-dwell bit = 0.
In linear sweep mode, when the profile pin transitions from low
to high, the RDW is applied to the input of the sweep
accumulator and the RSRR register is loaded into the sweep rate
timer.
The RDW accumulates at the rate given by the ramp rate
(RSRR) until the output is equal to the CTW1 register value.
The sweep is then complete and the output is held constant in
frequency.
When the profile pin transitions from high to low, the FDW is
applied to the input of the sweep accumulator and the FSRR
register is loaded into the sweep rate timer.
The FDW accumulates at the rate given by the ramp rate
(FSRR) until the output is equal to the CTW0 register value.
The sweep is then complete and the output is held constant in
frequency.
See Figure 36 for the linear sweep block diagram. Figure 38
depicts a frequency sweep with no-dwell mode disabled. In this
mode, the output follows the state of the profile pin. A phase or
amplitude sweep works in the same manner.
LINEAR SWEEP—NO-DWELL MODE
If the linear sweep no-dwell bit is set (CFR <15>), the rising
sweep is started in an identical manner to the dwell linear
sweep mode. That is, upon detecting Logic 1 on the profile
input pin, the rising sweep action is initiated. The word
continues to sweep up at the rate set by the rising sweep ramp
rate at the resolution set by the rising delta tuning word until it
reaches the terminal value. Upon reaching the terminal value,
the output immediately reverts back to the starting point and
remains until Logic 1 is detected on the profile pin. Figure 37
shows an example of the no-dwell mode. The points labeled “A”
indicate where a rising edge is detected on the profile pin and
the points labeled “B” indicate where the AD9958 has
determined that the output has reached E0 and reverts to S0.
The falling ramp rate register and the falling delta word are
unused in this mode.
RATE TIME
LOAD CONTROL
LOGIC
LIMIT LOGIC TO
KEEP SWEEP BETWEEN
S0 AND E0
RAMP RATE TIMER:
8-BIT LOADABLE DOWN COUNTER
ACCUMULATOR RESET
LOGIC
0
1
MUX
0
1
MUX
0
1
MUX
PROFILE PIN
0
1
8
MUX
0
1
MUX
FDW
RDW
FSRR
RSRR
0
0
32
32
32
32
32
32
32
PROFILE PIN
Z
–1
CTW1
SWEEP ACCUMULATOR
SWEEP ADDER
CTW0
0
Figure 36. Linear Sweep Block Diagram
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9958BCPZ-REEL7 | 功能描述:IC DDS DUAL 10BIT DAC 56LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9959 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4 Channel 500MSPS DDS with 10-bit DACs |
| AD9959/PCBZ | 功能描述:BOARD EVALUATION FOR AD9959 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| AD9959/PCBZ | 制造商:Analog Devices 功能描述:AD9959, DDS, DAC, GUI, USB, EVALUATION B |
| AD9959/PCBZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:4-Channel, 500 MSPS DDS with 10-Bit DACs |
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