參數(shù)資料
型號(hào)： AD9958BCPZ
廠商： ANALOG DEVICES INC
元件分類： 模擬信號(hào)調(diào)理
英文描述： 2-Channel 500 MSPS DDS with 10-Bit DACs
中文描述： SPECIALTY ANALOG CIRCUIT, QCC56
封裝： 8 X 8 MM, LEAD FREE, MO-220-VLLD-2, LFCSP-56
文件頁(yè)數(shù)： 23/40頁(yè)
文件大小： 1051K
代理商： AD9958BCPZ
AD9958
The AD9958 has the ability to ramp up or ramp down (RU/RD)
the output amplitude (using the 10-bit output scalar) before and
after a linear sweep. If the RU/RD feature is desired, unused
profile pins or unused SDIO_1:3 pins can be configured for the
RU/RD operation.
Rev. 0 | Page 23 of 40
To enable linear sweep mode for a particular channel, AFP bits
(CFR <23:22>), modulation level bits (FR1 <9:8>), and the
linear sweep enable bit (CFR <14>) are programmed. The AFP
bits determine the type of linear sweep to be performed. The
modulation level bits must be set to 00 (2-level) for that specific
channel (see Table 19 and Table 20).
Table 19.
AFP
CFR <23:22>
CFR <14>
0
0
1
0
1
1
1
0
1
1
1
1
Linear Sweep Enable
Description
N/A
Amplitude sweep
Frequency sweep
Phase sweep
Table 20.
Modulation Level Bits FR1 <9:8>
0
0
1
1
Description
2-level modulation
4-level modulation
8-level modulation
16-level modulation
0
1
0
1
Setting the Slope of the Linear Sweep
The slope of the linear sweep is set by the intermediate step size
(delta-tuning word) between S0 and E0 and the time spent
(sweep ramp rate word) at each step. The resolution of the
delta-tuning word is 32 bits for frequency, 14 bits for phase, and
10 bits for amplitude. The resolution for the delta ramp rate
word is 8 bits.
In linear sweep, each channel is assigned a rising delta word
(RDW, Register 0x08) and a rising sweep ramp rate word
(RSRR, Register 0x07). These settings apply when sweeping up
towards E0. The falling delta word (FDW, Register 0x09) and
falling sweep ramp rate (FSRR, Register 0x07) apply when
sweeping down towards S0.
Note the sweep accumulator overflows if the rising or falling
delta word is too large. To prevent this from happening, the
magnitude of the rising or falling delta word should not be
greater than the difference between full scale and the E0 value
(full scale E0). For a frequency sweep, full scale is 2
31
1. For
a phase sweep, full scale is 2
14
1. For an amplitude sweep, full
scale is 2
10
1.
The following graph displays a linear sweep up and then down
using a profile pin. Note that the no-dwell bit is disabled; other-
wise, the sweep accumulator returns to 0 upon reaching EO.
(
L
RDW
RSRR
FSRR
f,p,a
FDW
TIME
SO
EO
PROFILE PIN
f,p,a
t
t
0
Figure 35.
For a piecemeal or a nonlinear transition between S0 and E0,
the delta-tuning words and ramp rate words can be repro-
grammed during the transition to produce the desired response.
The formulae for calculating the step size of RDW or FDW for
delta frequency, delta phase, or delta amplitude are as follows:
CLK
SYNC
RDW
2
32
f
_
×
=
(Hz)
°
×
=
360
2
14
RDW
ΔΦ
1024
2
10
×
=
RDW
a
(DAC full-scale current)
The formula for calculating delta time from RSRR or FSRR is
CLK
SYNC
RSRR
2
8
t
_
/
×
=
At 500 MSPS operation (SYNC_CLK =125 MHz), the maxi-
mum time interval between steps is 1/125 MHz × 256 = 2.048 μs.
The minimum time interval is (1/125 MHz) × 1 = 8.0 ns.
The sweep ramp rate block (timer) consists of a loadable 8-bit
down counter that continuously counts down from the loaded
value to 1. When the ramp rate timer equals 1, the proper ramp
rate value is loaded and the counter begins counting down to 1
again. This load and count down operation continues for as
long as the timer is enabled. However the count can be reloaded
before reaching 1 by either of the following two methods.
Method one is by changing the profile pin. When the profile pin
changes from Logic 0 to Logic 1, the rising sweep ramp rate
register (RSRR) value is loaded into the ramp rate timer, which
then proceeds to count down as normal. When the profile pin
changes from Logic 1 to Logic 0, the falling sweep ramp rate
register (FSRR) value is loaded into the ramp rate timer, which
then proceeds to count down as normal.
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