參數(shù)資料
型號(hào): AD9958
廠商: Analog Devices, Inc.
英文描述: 2-Channel 500 MSPS DDS with 10-Bit DACs
中文描述: 雙通道500 MSPS的DDS的10位DAC
文件頁數(shù): 28/40頁
文件大小: 1051K
代理商: AD9958
AD9958
I/O_UPDATE, SYNC_CLK, AND SYSTEM CLOCK
RELATIONSHIPS
I/O_UPDATE and SYNC_CLK are used together to transfer
data from the serial I/O buffer to the active registers in the
device. Data in the buffer is inactive.
Rev. 0 | Page 28 of 40
The I/O UPDATE is essentially over sampled by the
SYNC_CLK. Therefore, I/O_UPDATE must have a
minimum pulse width greater than one SYNC_CLK period.
The timing diagram shown in Figure 39 depicts when data in
the buffer is transferred to the active registers.
SYNC_CLK is a rising edge active signal. It is derived from
the system clock and a divide-by-4 frequency divider. The
SYNC_CLK is externally provided, which can be used to
synchronize external hardware to the AD9958’s internal clocks.
I/O_UPDATE initiates the start of a buffer transfer. It can be
sent synchronously or asynchronous relative to the SYNC_CLK.
If the set-up time between these signals is met, then constant
latency (pipeline) to the DAC output exists. For example, if
repetitive changes to phase offset via the SPI port are desired,
the latency of those changes to the DAC output is constant,
otherwise a time uncertainty of 1 SYNC_CLK period is present.
SYNC_CLK
SYSCLK
A
B
DATA 2
DATA 3
DATA 1
DATA IN
REGISTERS
DATA IN
I/O BUFFERS
DATA 1
DATA 2
DATA 3
I/O UPDATE
THE DEVICE REGISTERS AN I/O UPDATE AT POINT A. THE DATA IS TRANSFERRED FROM THE ASYNCHRONOUSLY LOADED I/O BUFFERS AT POINT B.
0
Figure 39.
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