參數(shù)資料
型號： AD9958
廠商： Analog Devices, Inc.
英文描述： 2-Channel 500 MSPS DDS with 10-Bit DACs
中文描述： 雙通道500 MSPS的DDS的10位DAC
文件頁數(shù)： 19/40頁
文件大?。?/td> 1051K
代理商： AD9958
AD9958
Single-Tone Mode—Matched Pipeline Delay
In single-tone mode, the AD9958 offers matched pipeline delay
to the DAC input for all frequency, phase, and amplitude
changes. This avoids having to deal with different pipeline
delays between the three input ports for such applications. The
feature is enabled by asserting the match pipeline delay bit
found in the channel function register (CSR) (Register 0x03).
This feature is available in single-tone mode only.
Rev. 0 | Page 19 of 40
REFERENCE CLOCK MODES
The AD9958 supports multiple reference clock configurations
to generate the internal system clock. As an alterative to
clocking the part directly with a high frequency clock source,
the system clock may be generated using the internal, PLL-
based reference clock multiplier. An on-chip oscillator circuit is
also available for providing a low frequency reference signal by
connecting a crystal to the clock input pins. Enabling these
features allows the part to operate with a low frequency clock
source and still provide a high update rate for the DDS and
DAC. However, using the clock multiplier changes the output
phase noise characteristics. For best phase noise performance, a
clean, stable clock with a high slew is required. Refer to
Figure 19 and Figure 20.
Enabling the PLL allows multiplication of the reference clock
frequency from 4× to 20×, in integer steps. The PLL
multiplication value is represented by a 5-bit multiplier value.
These bits are located in the Function Register 1 (FR1),
bits <22:18>. Refer to the Register Map.
When FR1 <22:18> is programmed with values ranging from 4
to 20 (decimal) the clock multiplier is enabled. The integer
value in the register represents the multiplication factor. The
system clock rate with the clock multiplier enabled is equal to
the reference clock rate times the multiplication factor. If FR1
<22:18> is programmed with a value less than 4 or greater than
20 the clock multiplier is disabled and the multiplication factor
is effectively 1.
Whenever the PLL clock multiplier is enabled or the
multiplication value is changed, time should be allowed to lock
the PLL (typically 1 ms).
Note that the output frequency of the PLL is restricted to a
frequency range of 100 MHz to 500 MHz. However, there is a
VCO gain bit that must be used appropriately. The VCO gain
bit defines two ranges (low/high) of frequency output. The
VCO gain bit defaults to low (see Specifications for details).
The charge pump current in the PLL defaults to 75
μA.
This
setting typically produces the best phase noise characteristics.
Increasing charge pump current may degrade phase noise, but
decreases the lock time and changes the loop bandwidth.
Enabling the on-chip oscillator for crystal operation is per-
formed by driving the CLK_MODE_SEL (Pin 24) to logic high
(1.8 V logic). With the on-chip oscillator enabled, connection of
an external crystal to the REF_CLK and REF_CLKB inputs is
made producing a low frequency reference clock. The crystal’s
frequency must be in the range of 20 MHz to 30 MHz.
Table 4 summarizes the clock modes of operation. See the
Specifications section for more details.
Table 4.
CLK_MODE_SEL
Pin (24)
High = 1.8 V
logic
High = 1.8 V
logic
Low
FR1<22:18>
PLL, Bits = M
4 ≤ M ≤ 20
Oscillator
Enabled
Yes
System
Clock
(f
SYS CLK
)
f
SYS CLK
=
f
OSC
× M
f
SYS CLK
=
F
OSC
f
SYS CLK
=
F
REF CLK
×
M
f
SYS CLK
=
F
REF CLK
Min/Max
Freq. Range
(MHz)
100 < f
SYSCLK
< 500
20 < f
SYSCLK
< 30
100 < f
SYSCLK
< 500
M < 4 or
M > 20
4 ≤ M ≤ 20
Yes
No
Low
M < 4 or
M > 20
No
0 < f
SYS CLK
<
500
Reference Clock Input Circuitry
The reference clock input circuitry has two modes of operation
controlled by the logic state of Pin 24 (clock mode select). The
first mode (logic low) configures as an input buffer. In this
mode, the reference clock must be ac-coupled to the input due
to internal dc biasing. This mode supports either differential
or single-ended configurations. If single-ended mode is
chosen, the complementary reference clock input (Pin 23)
should be decoupled to AVDD or AGND via a 0.1 μF capacitor.
Figure 32 and Figure 34 exemplify typical reference clock
configurations for the AD9958.
1:1
BALUN
REF_CLK
PIN 23
REFERENCE
CLOCK
SOURCE
REF_CLK
PIN 22
50
0.1
μ
F
0.1
μ
F
0
Figure 32.
The reference clock inputs can also support an LVPECL or
PECL driver as the reference clock source.
REF_CLK
PIN 23
REF_CLK
PIN 22
0.1
μ
F
0.1
μ
F
LVPECL/
PECL
DRIVER
TERMINATION
0
Figure 33.
The second mode of operation (Pin 24 = logic high = 1.8 V)
provides an internal oscillator for crystal operation. In this
mode, both clock inputs are dc-coupled via the crystal leads and
bypassed. The range of crystal frequencies supported is from
20 MHz to 30 MHz. Figure 34 shows the configuration for
using a crystal.
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相關代理商/技術參數(shù)
參數(shù)描述
AD9958 PCB 制造商:Analog Devices 功能描述:EVAL BOARD ((NS))
AD9958/PCB 制造商:Analog Devices 功能描述:Evaluation Board For 2-Channel 500 MSPS DDS With 10-Bit DACs 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述:IC 10-BIT DAC DDS
AD9958/PCBZ 功能描述:BOARD EVALUATION FOR AD9958 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:AgileRF™ 標準包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源
AD9958/PCBZ 制造商:Analog Devices 功能描述:EVAL BOARD, AD9958 DIRECT DIGITAL SYNTHE
AD9958_08 制造商:AD 制造商全稱:Analog Devices 功能描述:2-Channel, 500 MSPS DDS with 10-Bit DACs
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