參數(shù)資料
型號(hào)： AD9958
廠商： Analog Devices, Inc.
英文描述： 2-Channel 500 MSPS DDS with 10-Bit DACs
中文描述： 雙通道500 MSPS的DDS的10位DAC
文件頁(yè)數(shù)： 27/40頁(yè)
文件大小： 1051K
代理商： AD9958
AD9958
SYNCHRONIZING MULTIPLE AD9958 DEVICES
The AD9958 allows easy synchronization of multiple AD9958
devices. At power-up the phase of SYNC_CLK can be offset
between multiple devices. To correct for the offset and align the
SYNC_CLK edges, there are three methods (one automatic
mode and two manual modes) of synchronizing SYNC_CLKs.
These modes force the internal state machines of multiple
devices to a known state, which aligns SYNC_CLKs.
Rev. 0 | Page 27 of 40
Any mismatch in REF_CLK phase between devices results in a
corresponding phase mismatch on the SYNC_CLKs.
AUTOMATIC MODE SYNCHRONIZATION
In automatic mode, multiple part synchronization is achieved
by connecting the SYNC_OUT pin on the master device to the
SYNC_IN pin of the slave device(s). Devices are configured as
master or slave through programming bits, accessible via the
serial port.
A configuration for synchronizing multiple AD9958/59 devices
in automatic mode is shown in the Application Circuits section.
In this configuration, the AD9510 provides coincident
REF_CLKs and SYNC_OUTs to all devices.
Operation
The first step is to program the master and slave devices for
their respective roles. Enabling the master device is performed
by writing its master enable bit (FR2 <6>) true. This causes the
SYNC_OUT of the master device to output a pulse that has a
pulse width equal to one system clock period and a frequency
equal to one fourth of the system clock frequency. Enabling
device(s) as slaves is performed by writing the slave enable bit
(FR2 <7>) true.
In automatic synchronizing mode, the slave device(s) sample
SYNC_OUT pulses from the master device and a comparison of
all state machines is made by the autosynchronization circuitry.
If the slave device(s) state machines are not identical to the
master, the slave device(s) state machines are stalled for one
system clock cycle. This procedure synchronizes the slave
device(s) within three SYNC_CLK periods.
Delay Time Between SYNC_OUT and SYNC_IN
When the delay between SYNC_OUT and SYNC_IN exceeds
one system clock period, phase offset bits (FR2 <1:0>) are used
to compensate. The default state of these bits is 00, which
implies that the SYNC_OUT of the master and the SYNC_IN of
the slave have a propagation delay of less than one system clock
period. If the propagation time is greater than one system clock
period, the time should be measured and the appropriate offset
programmed. Table 24 describes the delays required per system
clock offset value.
Table 24.
System Clock
Offset Value
00
01
10
11
Automatic Synchronization Status Bits
If a slave device falls out of sync, the sync status bit is set high.
This bit can be read through the serial port bit (FR2 <5>). It is
automatically cleared when read.
SYNC_OUT/SYNC_IN
Propagation Delay
0 ≤ delay ≤ 1
1 ≤ delay ≤ 2
2 ≤ delay ≤ 3
3 ≤ delay ≤ 4
The synchronization routine continues to operate regardless of
the state of the status bit. The status bit can be masked by
writing Logic 1 to the synchronization status mask bit
(FR2 <4>). If the status bit is masked, it is held low.
MANUAL SOFTWARE MODE SYNCHRONIZATION
The manual software mode is enabled by setting the manual
synchronization bit (FR1 <0>) to Logic 1 in a device. In this
mode, the I/O update that writes the Manual SW synchro-
nization bit to Logic 0 stalls the state machine of the clock
generator for one system clock cycle. Stalling the clock
generation state machine by one cycle changes the phase
relationship of SYNC_CLK between devices by one system
clock period (90°).
Note that the user may have to repeat this process until the
devices have their SYNC_CLK signals in phase. The SYNC_IN
input may be left floating since it has an internal pull-up. The
SYNC_OUT is not used.
The synchronization is complete when the master and slave(s)
devices have their SYNC_CLK signals in phase.
MANUAL HARDWARE MODE SYNCHRONIZATION
Manual hardware mode is enabled by setting the manual SW
synchronization bit (FR1 <1>) to Logic 1 in a device. In manual
HW synchronization mode, the SYNC_CLK stalls by one
system clock cycle each time a rising edge is detected on the
SYNC_IN input. Stalling SYNC_CLK’s state machine by one
cycle changes the phase relationship of SYNC_CLK between
devices by one system clock period (90°).
Note that the user may have to repeat the process until the
devices have their SYNC_CLK signals in phase. The SYNC_IN
input might be left floating since it has an internal pull-up. The
SYNC_OUT is not used.
The synchronization is complete when the master and slave(s)
devices have their SYNC_CLK signals in phase.
相關(guān)PDF資料
PDF描述
AD9958BCPZ 2-Channel 500 MSPS DDS with 10-Bit DACs
AD9970 14-Bit CCD Signal Processor with Precision Timing Generator
AD9971 12-Bit CCD Signal Processor with Precision Timing
AD9973 Dual-Channel, 14-Bit CCD Signal Processor with Precision Timing⑩ Core
AD9974 Dual-Channel, 14-Bit, CCD Signal Processor with Precision Timing⑩ Core
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9958 PCB 制造商:Analog Devices 功能描述:EVAL BOARD ((NS))
AD9958/PCB 制造商:Analog Devices 功能描述:Evaluation Board For 2-Channel 500 MSPS DDS With 10-Bit DACs 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述:IC 10-BIT DAC DDS
AD9958/PCBZ 功能描述:BOARD EVALUATION FOR AD9958 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:AgileRF™ 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源
AD9958/PCBZ 制造商:Analog Devices 功能描述:EVAL BOARD, AD9958 DIRECT DIGITAL SYNTHE
AD9958_08 制造商:AD 制造商全稱:Analog Devices 功能描述:2-Channel, 500 MSPS DDS with 10-Bit DACs
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*