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參數(shù)資料
| 型號(hào)： | AD9957BSVZ-REEL |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡(luò) |
| 英文描述： | 1 GSPS Quadrature Digital Upconverter with 18-Bit IQ Data Path and 14-Bit DAC |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP100 |
| 封裝： | ROHS COMPLIANT, MS-026AED-HD, TQFP-100 |
| 文件頁數(shù)： | 27/60頁 |
| 文件大小： | 840K |
| 代理商： | AD9957BSVZ-REEL |
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AD9957
LOAD/RETRIEVE RAM OPERATION
Loading or retrieving the RAM contents is a three-step process.
Rev. 0 | Page 27 of 60
1.
Program the RAM segment registers with start and end
addresses defining the boundaries of each independent
RAM segment.
2.
Toggle the RT pin with the appropriate transition to select
the desired RAM segment register.
3.
Using the serial I/O port, write (or read) the address range
specified by the selected RAM segment register.
Figure 40 shows the RAM block diagram when used for loading
or retrieve operations.
RAM
32
10
Q
STATE
MACHINE
SCLK
I/O_RESET
SDIO
CS
RT
END ADDRESS
START ADDRESS
10
10
ADDRESS STEP RATE
16
RAM MODE
3
CLK
BASEBAND DATA CLOCK
I
16
IS
Q
QS
DDS CLOCK
UP/DOWN COUNTER
I CHANNEL
Q CHANNEL
S
A
D
U/D
32
2
(MSBs)
(LSBs)
16
0
NOTES
1. NONESSENTIAL FUNCTIONAL COMPONENTS ARE RENDERED IN GRAY.
RAM
SEGMENT
REGISTERS
Figure 40. RAM Load/Retrieve Operation
During a load or retrieve operation, the state machine controls
an up/down counter to step through the required RAM locations.
The counter is synchronized with the serial I/O port so that the
serial/parallel conversion of the 32-bit words is correctly timed
with the generation of the appropriate RAM address to properly
execute the desired read or write operation. The up/down
counter always increments through the address range during
serial I/O port operations.
Because the RAM segment registers are completely independent,
it is possible to define overlapping address ranges. However,
doing so causes the overlapping address locations to be over-
written by the most recent write operation. It is recommended
that the user avoid defining overlapping address ranges.
RAM PLAYBACK OPERATION
When the RAM has been loaded, it can be used for playback
operation. The destination of the playback data is selected via
the RAM playback destination bit. The active RAM segment
register is selected by the appropriate transition of the RT pin.
The active RAM segment register directs the internal state
machine by defining the RAM address range occupied by the
data and the RAM playback mode. It also defines the playback
rate when the playback destination is the baseband scaling
multipliers.
Although RAM load/retrieve operations via the serial I/O port
take precedence over playback, it is recommended that the user
not attempt RAM access via the serial I/O port when the RAM
enable bit is set.
Figure 41 is a block diagram showing the functional compo-
nents used for RAM playback operation when the internal
destination is the baseband scaling multipliers.
RAM
32
10
Q
STATE
MACHINE
SCLK
I/O_RESET
SDIO
CS
RT
END ADDRESS
START ADDRESS
10
10
ADDRESS STEP RATE
16
RAM MODE
3
CLK
BASEBAND DATA CLOCK
I
16
IS
Q
QS
DDS CLOCK
UP/DOWN COUNTER
I CHANNEL
Q CHANNEL
RAM
SEGMENT
REGISTERS
S
A
D
U/D
32
2
(MSBs)
(LSBs)
16
0
NOTES
1. NONESSENTIAL FUNCTIONAL COMPONENTS ARE RENDERED IN GRAY.
Figure 41. RAM Playback to Baseband Scaling Multipliers
During playback to the baseband scaling multipliers, the
address step rate word in the active RAM segment register sets
the rate at which RAM data samples are delivered to the
multipliers. The following equations define the RAM sample
rate and sample interval (Δt).
f
Rate
Sample
RAM
4
RM
t
=
Δ
RM
SYSCLK
=
SYSCLK
f
4
where:
R
is the rate interpolation factor for the CCI filter.
M
is the 16-bit value of the address step rate word stored in the
active RAM segment register.
If the RAM enable bit is set and the baseband scaling multi-
pliers are selected as the playback destination, then assertion
of an I/O update or profile change causes the multipliers to be
driven with a static value of zero. A subsequent state change on
the RT pin causes the multipliers to be driven by the data played
back from the RAM instead of the static zero value.
Figure 42 is a block diagram showing RAM playback operation
when the internal destination is the baseband data path. During
playback to the baseband data path, the state machine
increments/decrements the RAM address at the baseband data
rate (the address step rate is ignored by the state machine).
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