參數(shù)資料
型號(hào)： AD9957BSVZ-REEL
廠商： ANALOG DEVICES INC
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： 1 GSPS Quadrature Digital Upconverter with 18-Bit IQ Data Path and 14-Bit DAC
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP100
封裝： ROHS COMPLIANT, MS-026AED-HD, TQFP-100
文件頁(yè)數(shù)： 2/60頁(yè)
文件大?。?/td> 840K
代理商： AD9957BSVZ-REEL
AD9957
TABLE OF CONTENTS
Features..............................................................................................1
Rev. 0 | Page 2 of 60
Applications.......................................................................................1
General Description.........................................................................1
Functional Block Diagram..............................................................1
Specifications.....................................................................................4
Electrical Specifications...............................................................4
Absolute Maximum Ratings............................................................7
ESD Caution..................................................................................7
Pin Configuration and Function Descriptions.............................8
Typical Performance Characteristics...........................................11
Modes of Operation.......................................................................15
Overview......................................................................................15
Quadrature Modulation Mode.................................................16
BlackFin Interface (BFI)............................................................17
Interpolating DAC Mode ..........................................................18
Single Tone Mode.......................................................................19
Signal Processing............................................................................20
Parallel Data Clock (PDCLK)...................................................20
Transmit Enable Pin (TxEnable)..............................................20
Input Data Assembler................................................................21
Inverse CCI Filter.......................................................................22
Fixed Interpolator (4×)..............................................................22
Programmable Interpolating Filter..........................................23
Quadrature Modulator ..............................................................23
DDS Core.....................................................................................24
Inverse Sinc Filter.......................................................................24
Output Scale Factor (OSF)........................................................25
14-Bit DAC..................................................................................25
Auxiliary DAC........................................................................25
RAM Control..................................................................................26
RAM Overview...........................................................................26
RAM Segment Registers............................................................26
RAM State Machine................................................................... 26
RAM Trigger (RT) Pin............................................................... 26
Load/Retrieve RAM Operation................................................ 27
RAM Playback Operation......................................................... 27
Overview of RAM Playback Modes......................................... 28
RAM Ramp-Up Mode........................................................... 28
RAM Bidirectional Ramp Mode.......................................... 29
RAM Continuous Bidirectional Ramp Mode.................... 31
RAM Continuous Recirculate Mode................................... 32
Clock Input (REF_CLK)................................................................ 33
REFCLK Overview..................................................................... 33
Crystal Driven REF_CLK ......................................................... 33
Direct Driven REF_CLK........................................................... 33
Phase-Locked Loop (PLL) Multiplier...................................... 34
PLL Charge Pump...................................................................... 35
External PLL Loop Filter Components................................... 35
PLL Lock Indication .................................................................. 35
Additional Features........................................................................ 36
Output Shift Keying (OSK)....................................................... 36
Manual OSK............................................................................ 36
Automatic OSK....................................................................... 36
Profiles......................................................................................... 37
I/O_UPDATE Pin...................................................................... 37
Automatic I/O Update............................................................... 37
Power-Down Control ................................................................ 38
General-Purpose I/O (GPIO) Port.......................................... 38
Synchronization of Multiple Devices........................................... 39
Serial Programming....................................................................... 42
Control Interface—Serial I/O................................................... 42
General Serial I/O Operation................................................... 42
Instruction Byte.......................................................................... 42
Instruction Byte Information Bit Map................................ 42
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