參數(shù)資料
型號(hào)： AD9957BSVZ-REEL
廠商： ANALOG DEVICES INC
元件分類(lèi)： 通信及網(wǎng)絡(luò)
英文描述： 1 GSPS Quadrature Digital Upconverter with 18-Bit IQ Data Path and 14-Bit DAC
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP100
封裝： ROHS COMPLIANT, MS-026AED-HD, TQFP-100
文件頁(yè)數(shù)： 21/60頁(yè)
文件大小： 840K
代理商： AD9957BSVZ-REEL
AD9957
Rev. 0 | Page 21 of 60
t
DH
I
0
TxENABLE
PDCLK
D<13:0>
I
K
I
K – 1
I
3
I
2
I
1
0
t
DH
t
DS
t
DS
Figure 30. 18-Bit Parallel Port Timing Diagram—Interpolating DAC Mode
t
DH
I
0
TxENABLE
PDCLK
D<13:0>
Q
N
I
N
Q
1
I
1
Q
0
0
t
DH
t
DS
t
DS
Figure 31. 18-Bit Parallel Port Timing Diagram—Quadrature Modulation Mode
TxENABLE
PDCLK
I DATA
Q DATA
Q
0
Q
1
Q
2
Q
3
Q
4
Q
6
Q
5
Q
7
Q
8
Q
9
Q
10
Q
11
Q
12
Q
13
Q
14
Q
15
I
0
I
1
I
2
I
3
I
4
I
6
I
5
I
7
I
8
I
9
I
10
I
11
I
12
I
13
I
14
I
15
I
16n – 1
Q
16n – 1
0
Figure 32. Dual Serial I/Q Bit Stream Timing Diagram, BFI Mode
INPUT DATA ASSEMBLER
The input to the AD9957 is an 18-bit parallel data port in
QDUC or interpolating DAC modes. In BFI mode, it operates
as a dual serial data port.
In QDUC mode, it is assumed that two consecutive 18-bit
words represent the real (I) and imaginary (Q) parts of a
complex number of the form, I + jQ. The 18-bit words are
supplied to the input of the AD9957 at a rate of
f
f
PDCLK
2
R
SYSCLK
=
for QDUC mode
where:
f
SYSCLK
(for all of the PDCLK equations in this section) is the
sample rate of the DAC.
R
(for all of the PDCLK equations in this section) is the
interpolation factor of the programmable interpolation filter.
When the PDCLK rate control bit is active in QDUC mode,
however, the frequency of PDCLK becomes
f
f
PDCLK
4
R
SYSCLK
=
with PDCLK rate control active
In the interpolating DAC mode, the rate of PDCLK is the same
as QDUC mode with the PDCLK rate control bit active, that is
f
f
PDCLK
4
R
SYSCLK
=
for interpolating DAC mode
In BFI mode, the 18-bit parallel input converts to a dual serial
input. That is, one pin is assigned as the serial input for the I-words
and one pin is assigned as the serial input for the Q-words. The
other 16 pins are not used. Furthermore, each I- and Q-word
has a 16-bit resolution. f
PDCLK
is the bit rate of the I- and Q-data
streams and is given by
f
f
(for BFI mode)
R
SYSCLK
PDCLK
=
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