參數(shù)資料
型號(hào)： AD9957/PCBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 51/64頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL AD9957 QUADRATURE MOD
產(chǎn)品培訓(xùn)模塊： Direct Digital Synthesis Tutorial Series (1 of 7): Introduction
Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action
Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter
Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction
Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter
Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator
設(shè)計(jì)資源： AD9957 Eval Brd Schematic
AD9957 BOM
AD9957 Gerber Files
標(biāo)準(zhǔn)包裝： 1
系列： AgileRF™
主要目的： 計(jì)時(shí)：DDS 調(diào)制器
嵌入式： 否
已用 IC / 零件： AD9957
主要屬性： 14 位數(shù)模轉(zhuǎn)換器，32 位調(diào)節(jié)字寬
次要屬性： 1GHz 圖形用戶界面
已供物品： 板，軟件
產(chǎn)品目錄頁(yè)面： 552 (CN2011-ZH PDF)
相關(guān)產(chǎn)品： AD9957BSVZ-ND - IC DDS 1GSPS 14BIT IQ 100TQFP
AD9957BSVZ-REEL-ND - IC DDS 1GSPS 14BIT IQ 100TQFP
Data Sheet
AD9957
Rev. C | Page 55 of 64
REGISTER BIT DESCRIPTIONS
The serial I/O port registers span an address range of 0 to 25
(0x00 to 0x19 in hexadecimal notation). This represents a total
of 26 registers. However, six of these registers are unused, yielding
a total of 20 available registers. The unused registers are 7, 8, 11
to 13, and 23 (0x07 to 0x08, 0x0B to 0x0D, and 0x17).
The number of bytes assigned to the registers varies. That is, the
registers are not of uniform depth; each contains the number
of bytes necessary for its particular function. Additionally, the
registers are assigned names according to their functionality.
In some cases, a register is given a mnemonic descriptor. For
example, the register at Serial Address 0x00 is named Control
Function Register 1 and is assigned the mnemonic CFR1.
The following section provides a detailed description of each bit
in the AD9957 register map. For cases in which a group of bits
serve a specific function, the entire group is considered as a
binary word and described in aggregate.
This section is organized in sequential order of the serial
addresses of the registers. Following each subheading are the
individual bit descriptions for that particular register. The
location of the bit(s) in the register are indicated by <A> or
<A:B>, where A and B are bit numbers. The notation, <A:B>,
specifies a range of bits from most significant to least significant
bit position. For example, <5:2> means bit positions 5 down to
2, inclusive, with Bit 0 identifying the LSB of the register.
Unless otherwise stated, programmed bits are not transferred to
their internal destinations until the assertion of an I/O update or
profile change.
Control Function Register 1 (CFR1)
Address 0x00, four bytes are assigned to this register.
Table 18. Bit Descriptions for CFR1 Register
Bit (s)
Mnemonic
Description
31
RAM Enable
0: disables RAM playback functionality (default).
1: enables RAM playback functionality.
30:29
Open
28
RAM Playback
Destination
Ineffective unless CFR1<31> = 1.
0: RAM playback data routed to baseband scaling multipliers (default).
1: RAM playback data routed to baseband I/Q data path.
27:26
Open
25:24
Operating Mode
00: quadrature modulation mode (default).
01: single tone mode.
1x: interpolating DAC mode.
23
Manual OSK
External Control
Ineffective unless CFR1<9:8> = 10b.
0: OSK pin inoperative (default).
1: OSK pin enabled for manual OSK control (see the Output Shift Keying (OSK) section).
22
Inverse Sinc Filter
Enable
0: inverse sinc filter bypassed (default).
1: inverse sinc filter active.
21
Clear CCI
This bit is automatically cleared by the serial I/O port controller. This operation requires several internal clock
cycles to complete, during which time the data supplied to the CCI input by the baseband signal chain is
ignored. The inputs are forced to all zeros to flush the CCI data path, after which the CCI accumulators are reset.
0: normal operation of the CCI filter (default).
1: initiates an asynchronous reset of the accumulators in the CCI filter.
20:17
Open
16
Select DDS Sine
Output
Ineffective unless CFR1<25:24> = 01b.
0: cosine output of the DDS is selected (default).
1: sine output of the DDS is selected.
15:14
Open
13
Autoclear Phase
Accumulator
0: normal operation of the DDS phase accumulator (default).
1: synchronously resets the DDS phase accumulator any time I/O_UPDATE is asserted or a profile
change occurs.
12
Open
11
Clear Phase
Accumulator
0: normal operation of the DDS phase accumulator (default).
1: asynchronous, static reset of the DDS phase accumulator.
10
Load ARR @ I/O
Update
0: normal operation of the OSK amplitude ramp rate timer (default).
1: OSK amplitude ramp rate timer reloaded any time I/O_UPDATE is asserted or a profile change occurs.
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