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參數(shù)資料
| 型號(hào)： | AD9957/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 14/64頁(yè) |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL AD9957 QUADRATURE MOD |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 設(shè)計(jì)資源： | AD9957 Eval Brd Schematic AD9957 BOM AD9957 Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | AgileRF™ |
| 主要目的： | 計(jì)時(shí)：DDS 調(diào)制器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9957 |
| 主要屬性： | 14 位數(shù)模轉(zhuǎn)換器，32 位調(diào)節(jié)字寬 |
| 次要屬性： | 1GHz 圖形用戶界面 |
| 已供物品： | 板，軟件 |
| 產(chǎn)品目錄頁(yè)面： | 552 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | AD9957BSVZ-ND - IC DDS 1GSPS 14BIT IQ 100TQFP AD9957BSVZ-REEL-ND - IC DDS 1GSPS 14BIT IQ 100TQFP |
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Data Sheet
AD9957
Rev. C | Page 21 of 64
SIGNAL PROCESSING
For a better understanding of the operation of the AD9957, it
is helpful to follow the signal path in quadrature modulation
mode from the parallel data port to the output of the DAC,
examining the function of each block (see Figure 26).
The internal system clock (SYSCLK) signal that generates from
the timing source provided to the REF_CLK pins provides all
timing within the AD9957.
PARALLEL DATA CLOCK (PDCLK)
The AD9957 generates a signal on the PDCLK pin, which is a
clock signal that runs at the sample rate of the parallel data port.
PDCLK serves as a data clock for the parallel port in QDUC
and interpolating DAC modes; in BFI mode, it is a bit clock.
Normally, the device uses the rising edges on PDCLK to latch
the user-supplied data into the data port. Alternatively, the
PDCLK Invert bit selects the falling edges as the active edges.
Furthermore, the PDCLK enable bit is used to switch off the
PDCLK signal. Even when the output signal is turned off via the
PDCLK enable bit, PDCLK continues to operate internally. The
device uses PDCLK internally to capture parallel data. Note that
PDCLK is Logic 0 when disabled.
In QDUC mode, the AD9957 expects alternating I- and Q-
data-words at the parallel port (see Figure 31). Each active edge
of PDCLK captures one 18-bit word; therefore, there are two
PDCLK cycles per I/Q pair. In BFI mode, the AD9957 expects
two serial bit streams, each segmented into 16-bit words with
PDCLK indicating each new bit. In either case, the output clock
In QDUC applications that require a consistent timing relation-
ship between the internal SYSCLK signal and the PDCLK signal,
the PDCLK rate control bit is used to slightly alter the operation
of PDCLK. When this bit is set, the PDCLK rate is reduced by
a factor of two. This causes rising edges on PDCLK to latch
incoming I-words and falling edges to latch incoming Q-words.
Again, the edge polarity assignment is reversible via the PDCLK
Invert bit.
TRANSMIT ENABLE PIN (TxENABLE)
The AD9957 accepts a user-generated signal applied to the
TxENABLE pin that gates the user supplied data. Polarity of
the TxENABLE pin is set using the TxENABLE invert bit (see
the Register Map section for details). When TxENABLE is true,
the device latches data into the device on the expected edge of
PDCLK (based on the PDCLK invert bit). When TxENABLE
is false, the device ignores the data supplied to the port, even
though the PDCLK may continue to operate. Furthermore,
when the TxENABLE pin is held false, then the device either
forces the 18-bit data-words to Logic 0s, or it retains the last
value present on the data port prior to TxENABLE switching
to the false state (see the data assembler hold last value bit in
the Register Map section).
Alternatively, rather than operating the TxENABLE pin as a
gate for framing bursts of data, it can be driven with a clock
signal operating at the parallel port data rate. When driven by
a clock signal, the transition from the false to true state must
meet the required setup and hold times on each cycle to ensure
proper operation.
In QDUC mode, on the false-to-true edge of TxENABLE, the
device is ready to receive the first I-word. The first I-word is
latched into the device coincident with the active edge of PDCLK.
The next active edge of PDCLK latches in a Q-word, and so on,
until TxENABLE is returned to a static false state. The user may
reverse the ordering of the I- and Q-words via the Q-First Data
Pairing bit. Furthermore, the user must ensure that an even
number of data words are delivered to the device as it must
capture both an I- and a Q-word before the data is processed
along the signal chain.
In interpolating DAC mode, TxENABLE operation is similar to
QDUC mode, but without the need for I/Q data pairing; the
even-number-of-PDCLK-cycles rule does not apply.
In BFI mode, operation of the TxENABLE pin is similar except
that instead of the false-to-true edge marking the first I-word,
it marks the first I and Q bits in a serial frame. The user must
ensure that all 16-bits of a serial frame are delivered because the
device must capture a full 16-bit I- and Q-word before the data
is processed along the signal chain.
The timing relationships between TxENABLE, PDCLK, and
DATA are shown in Figure 30, Figure 31, and Figure 32.
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| ATWEBDVK-02RC | KIT DEV TCP/IP AT89C51RD2 REMOTE |
| KSZ8862-10FL-EVAL | BOARD EVALUATION KSZ8862-10FL |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9958 | 制造商:AD 制造商全稱:Analog Devices 功能描述:2-Channel 500 MSPS DDS with 10-Bit DACs |
| AD9958 PCB | 制造商:Analog Devices 功能描述:EVAL BOARD ((NS)) |
| AD9958/PCB | 制造商:Analog Devices 功能描述:Evaluation Board For 2-Channel 500 MSPS DDS With 10-Bit DACs 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述:IC 10-BIT DAC DDS |
| AD9958/PCBZ | 功能描述:BOARD EVALUATION FOR AD9958 RoHS:是 類別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:AgileRF™ 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| AD9958/PCBZ | 制造商:Analog Devices 功能描述:EVAL BOARD, AD9958 DIRECT DIGITAL SYNTHE |
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