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參數(shù)資料
| 型號(hào)： | AD9957/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁(yè)數(shù)： | 36/64頁(yè) |
| 文件大小： | 0K |
| 描述： | BOARD EVAL AD9957 QUADRATURE MOD |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 設(shè)計(jì)資源： | AD9957 Eval Brd Schematic AD9957 BOM AD9957 Gerber Files |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | AgileRF™ |
| 主要目的： | 計(jì)時(shí)：DDS 調(diào)制器 |
| 嵌入式： | 否 |
| 已用 IC / 零件： | AD9957 |
| 主要屬性： | 14 位數(shù)模轉(zhuǎn)換器，32 位調(diào)節(jié)字寬 |
| 次要屬性： | 1GHz 圖形用戶(hù)界面 |
| 已供物品： | 板，軟件 |
| 產(chǎn)品目錄頁(yè)面： | 552 (CN2011-ZH PDF) |
| 相關(guān)產(chǎn)品： | AD9957BSVZ-ND - IC DDS 1GSPS 14BIT IQ 100TQFP AD9957BSVZ-REEL-ND - IC DDS 1GSPS 14BIT IQ 100TQFP |
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Data Sheet
AD9957
Rev. C | Page 41 of 64
SYSCLK
SYNC
GENERATOR
ENABLE
SYNC
GENERATOR
DELAY
SYNC
POLARITY
SYNC_OUT
0
1
D Q
R
PROGAMMABLE
DELAY
÷16
÷2R
5
9
10
LVDS
DRIVER
06384-
033
Figure 56. Sync Generator
The sync generator produces an LVDS-compatible clock signal
with a 50% duty cycle that appears at the SYNC_OUT pins. The
frequency of the SYNC_OUT signal can be one of two possible
rates. With the AD9957 programmed for any of the following
modes:
Single tone mode
Quadrature modulation mode with the CCI filter bypassed
(that is, interpolation factor is 1)
Interpolating DAC mode with the CCI filter bypassed (that
is, interpolation factor is 1)
The frequency of SYNC_OUT is given by:
16
_
SYSCLK
OUT
SYNC
f
=
With the AD9957 programmed for the QDUC or interpolating
DAC mode and with the CCI filter not bypassed (that is, R>1)
the frequency of SYNC_OUT is given by
R
f
SYSCLK
OUT
SYNC
32
_
=
where R is the programmed interpolation factor of the CCI filter.
The signal at the SYNC_OUT pins is edge aligned with either
the rising or falling edge of the internal SYSCLK signal as deter-
mined by the Sync Polarity bit. Because the SYNC_OUT signal is
synchronized with the internal SYSCLK of the master device, the
master device SYSCLK serves as the reference timing source for
all slave devices.
The user can adjust the output delay of the SYNC_OUT signal
in steps of ~75 ps by programming the 5-bit sync generator
delay word via the serial I/O port. The programmable output
delay facilitates added edge timing flexibility to the overall
synchronization mechanism.
SYNC RECEIVER
The sync receiver block (shown in Figure 57) is activated via the
Sync Receiver Enable bit. The sync receiver consists of three
subsections: the input delay and edge detection block, the
internal clock generator block, and the setup-and-hold valida-
tion block.
The clock generator block remains operational even when the
sync receiver is not enabled.
The sync receiver accepts an LVDS-compatible signal at the
SYNC_IN pins. Typically, the signal applied to the SYNC_IN
pins originates from the SYNC_OUT of another AD9957
functioning as a master timing unit. The sync receiver expects a
periodic synchronization pulse that meets certain frequency
requirements based on the operating mode of the AD9957.
When programmed for single tone mode, the frequency of
SYNC_IN must satisfy
M
f
SYSCLK
IN
SYNC
4
_
=
where M is any integer greater than zero. When programmed
for quadrature modulation mode (using the parallel data port)
or interpolating DAC mode, the frequency of SYNC_IN must
satisfy
(
)
M
R
f
SYSCLK
IN
SYNC
+
=
16
_
where R is the programmed CCI interpolation factor and M is
any integer greater than or equal to zero. When programmed
for quadrature modulation mode using the BlackFin interface,
the frequency of SYNC_IN must satisfy
(
)
M
R
f
SYSCLK
IN
SYNC
+
=
32
_
where R is the programmed CCI interpolation factor and M is
any integer greater than or equal to zero.
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9958 | 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:2-Channel 500 MSPS DDS with 10-Bit DACs |
| AD9958 PCB | 制造商:Analog Devices 功能描述:EVAL BOARD ((NS)) |
| AD9958/PCB | 制造商:Analog Devices 功能描述:Evaluation Board For 2-Channel 500 MSPS DDS With 10-Bit DACs 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述:IC 10-BIT DAC DDS |
| AD9958/PCBZ | 功能描述:BOARD EVALUATION FOR AD9958 RoHS:是 類(lèi)別:編程器，開(kāi)發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:AgileRF™ 標(biāo)準(zhǔn)包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| AD9958/PCBZ | 制造商:Analog Devices 功能描述:EVAL BOARD, AD9958 DIRECT DIGITAL SYNTHE |
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