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參數(shù)資料
| 型號： | AD9956-VCO/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 25/32頁 |
| 文件大小： | 0K |
| 描述： | BOARD EVAL 14BIT 1.8V 48LFCSP |
| 產(chǎn)品培訓模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 標準包裝： | 1 |
| 系列： | AgileRF™ |
| 主要目的： | 計時，直接數(shù)字合成（DDS） |
| 已用 IC / 零件： | AD9956 |
| 已供物品： | 板 |
| 相關產(chǎn)品： | AD9956YCPZ-ND - IC SYNTHESIZER 1.8V 48LFCSP AD9956YCPZ-REEL7-ND - IC SYNTHESIZER 1.8V 48LFCSP |
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AD9956
Rev. A | Page 31 of 32
CFR2<15:12> PLLREF Divider Control Bits (÷N)
These 4 bits set the PLLREF divider (÷N) ratio where N is a
value equal to 1 to 16. CFR2<15:12> = 0000 means that
N = 1 and CFR2<15:12> = 1111 means that N = 16, or simply,
N = CFR2<15:12> + 1.
CFR2<15:12> =
N =
CFR2<15:12> =
N =
0000
1
1000
9
0001
2
1001
10
0010
3
1010
11
0011
4
1011
12
0100
5
1100
13
0101
6
1101
14
0110
7
1110
15
0111
8
1111
16
CFR2<11:8> PLLREF Divider Control Bits (÷M)
These 4 bits set the PLLOSC divider (÷M) ratio where
M is a value equal to 1 to 16. CFR2<11:8> = 0000 means
that M = 1 and CFR2<11:8> = 1111 means that M = 16, or
M = CFR2<11:8> + 1.
CFR2<11:8> =
M =
CFR2<11:8> =
M =
0000
1
1000
9
0001
2
1001
10
0010
3
1010
11
0011
4
1011
12
0100
5
1100
13
0101
6
1101
14
0110
7
1110
15
0111
8
1111
16
CFR2<7:6> Open
Unused locations. Write a Logic 0.
CFR2<5> CP Polarity
This bit sets the polarity of the charge pump, in response to a
ground referenced or a supply referenced VCO.
CFR2<5> = 0 (default). The charge pump is configured to
operate with a supply referenced VCO. If PLLOSC lags PLLREF,
the charge pump will attempt to drive the VCO control node
voltage higher. If PLLOSC leads PLLREF, the charge pump will
attempt to drive the VCO control node voltage lower.
CFR2<5> = 1. The charge pump is configured to operate with a
ground referenced VCO. If PLLOSC lags PLLREF, the charge
pump will attempt to drive the VCO control node voltage lower.
If PLLOSC leads PLLREF, the charge pump will attempt to drive
the VCO control node voltage higher.
CFR2<4> Charge Pump Full Power-Down
This bit, when set, will put the charge pump into a full power-
down mode.
CFR2<4> = 0 (default). The charge pump is powered on and
operating normally.
CFR2<4> = 1. The charge pump is completely powered down.
CFR2<3> Charge Pump Quick Power-Down
Rather than power down the charge pump, which can take a
long time to recover from, a quick power-down mode, which
powers down only the charge pump output buffer, is included.
While this doesn’t reduce the power consumption significantly,
it does shut off the output to the charge pump and allows it to
come back on in a rapidly.
CFR2<3> = 0 (default). The charge pump is powered on and
operating normally.
CFR2<3> = 1. The charge pump is on and running, but the
output buffer is powered down.
CFR2<2:0> Charge Pump Current Scale.
A base output current from the charge pump is determined by a
resistor connected from the CP_RSET pin to ground (see the
PLL Circuitry section). However, it is possible to multiply the
charge pump output current by a value from 1:8 by programming
these bits. The charge pump output current is scaled by
CFR2<2:0> +1.
CFR2<2:0> = 000 (default). Scale factor = 1 to CFR2<2:0> = 111 (8).
CFR2<2:0>
Scale Factor
000
1
001
2
010
3
011
4
100
5
101
6
110
7
111
8
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9956XCPZ | 制造商:Analog Devices 功能描述:DGTL SYNTHESIZER 48LFCSP EP - Tape and Reel |
| AD9956YCP | 制造商:Analog Devices 功能描述:- Trays |
| AD9956YCPZ | 功能描述:IC SYNTHESIZER 1.8V 48LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9956YCPZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:2.7 GHz DDS-Based AgileRF |
| AD9956YCPZ-REEL1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:2.7 GHz DDS-Based AgileRF |
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