- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄16826 > AD9956-VCO/PCBZ (Analog Devices Inc)BOARD EVAL 14BIT 1.8V 48LFCSP PDF資料下載
參數(shù)資料
| 型號： | AD9956-VCO/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 21/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL 14BIT 1.8V 48LFCSP |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | AgileRF™ |
| 主要目的： | 計時，直接數(shù)字合成（DDS） |
| 已用 IC / 零件： | AD9956 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | AD9956YCPZ-ND - IC SYNTHESIZER 1.8V 48LFCSP AD9956YCPZ-REEL7-ND - IC SYNTHESIZER 1.8V 48LFCSP |
第1頁第2頁第3頁第4頁第5頁第6頁第7頁第8頁第9頁第10頁第11頁第12頁第13頁第14頁第15頁第16頁第17頁第18頁第19頁第20頁當(dāng)前第21頁第22頁第23頁第24頁第25頁第26頁第27頁第28頁第29頁第30頁第31頁第32頁
AD9956
Rev. A | Page 28 of 32
The AD9956 phase frequency detector has an on-chip oscillator
circuit. When enabled, the reference input to the phase fre-
quency detector (PLLREF/PLLREF
CFR1 <17> Linear Sweep Enable
This bit turns on the frequency accumulator, which enables the
DDS to perform linear sweeping.
CFR1<17> = 0 (default). The DDS generates frequencies in
single-tone mode.
CFR1<17> = 1. The DDS uses the frequency accumulator to
sweep the frequency tuning word being sent to the phase
accumulator according to the values set in the delta frequency
tuning word and delta frequency ramp rate registers. For a
detailed explanation of this mode, see the linear sweep mode of
operation section.
CFR1 <16> Linear Sweep No Dwell
This bit dictates the behavior of the DDS core upon completion
of a linear sweep.
CFR1<16> = 0 (default). Upon reaching the upper value of the
sweep (FTW1), the DDS holds at the frequency value stored in
FTW1.
CFR1<16> = 1. Upon reaching the upper value of the sweep
(FTW1), the DDS returns to the initial value in the sweep
(FTW0) and continues to output that frequency until a new
sweep is initiated (by bringing PS0 low and then high).
CFR1 <15> LSB First Serial Data Mode
The serial data transfer to the device can be either MSB first or
LSB first. This bit controls that operation.
CFR1<15> = 0 (default). Serial data transfer to the device is in
MSB first mode.
CFR1<15> = 1. Serial data transfer to the device is in LSB first
mode.
CFR1<14> SDI/O Input Only (3-Wire Serial Data Mode)
The serial port on the AD9956 can act in 2-wire mode (SCLK
and SDI/O) or 3-wire mode (SCLK, SDI/O, and SDO). This bit
toggles the serial port between these two modes.
CFR1<14> = 0 (default). Serial data transfer to the device is in
2-wire mode. The SDI/O pin is bidirectional.
CFR1<14> = 1. Serial data transfer to the device is in 3-wire
mode. The SDI/O pin is input only.
CFR1<13:8> Open
Unused locations. Write a Logic 0.
CFR1<7> Digital Power-Down
This bit powers down the digital circuitry not directly related to
the I/O port. The I/O port functionality is not suspended, re-
gardless of the state of this bit.
CFR1<7> = 0 (default). Digital logic operating as normal.
CFR1<7> = 1. All digital logic not directly related to the I/O
port is powered down. Internal digital clocks are suspended.
CFR1<6> Phase Frequency Detector Input Power-Down
This bit controls the input buffers on the phase frequency detec-
tor. It provides a way to gate external signals from the phase
frequency detector itself.
CFR1<6> = 0 (default). Phase frequency detector input buffers
are functioning normally.
CFR1<6> = 1. Phase frequency detector input buffers are pow-
ered down, isolating the phase frequency detector from the
outside world.
CFR1<5> PLLREF Crystal Enable
) can be driven by a crystal.
CFR1<5> = 0 (default). Phase frequency detector reference
input operates as a standard analog input.
CFR1<5> = 1. Reference input oscillator circuit is enabled,
allowing the use of a crystal for the reference of the phase
frequency detector.
CFR1<4> SYNC_CLK Disable
If synchronization of multiple devices is not required, the spec-
tral energy resulting from this signal can be reduced by gating
the output buffer off. This function gates the internal clock ref-
erence SYNC_CLK (SYSCLK/4) off of the SYNC_OUT pin.
CFR1<4> = 0 (default). SYNC_CLK signal is present on the
SYNC_OUT pin and is ready to be ported to other devices.
CFR1<4> = 1. SYNC_CLK signal is gated off, putting the
SYNC_OUT pin into a high impedance state.
CFR1<3> Automatic Synchronization
One of the synchronization modes of the AD9956 forces the
DDS core to derive the internal reference from an external ref-
erence supplied on the SYNC_IN pin. For details on synchroni-
zation modes for the DDS core, see the Synchronization Modes
for Multiple Devices section.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| GEM22DRKF | CONN EDGECARD 44POS DIP .156 SLD |
| 362A024-4/86-0 | BOOT MOLDED |
| AD9956/PCBZ | BOARD EVAL FOR AD9956 |
| 0210391089 | CABLE JUMPER 1MM .203M 37POS |
| 570-003-744-200 | ASSEMBLY RECEPT 3POS WATERPROOF |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9956XCPZ | 制造商:Analog Devices 功能描述:DGTL SYNTHESIZER 48LFCSP EP - Tape and Reel |
| AD9956YCP | 制造商:Analog Devices 功能描述:- Trays |
| AD9956YCPZ | 功能描述:IC SYNTHESIZER 1.8V 48LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9956YCPZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:2.7 GHz DDS-Based AgileRF |
| AD9956YCPZ-REEL1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:2.7 GHz DDS-Based AgileRF |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。