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參數(shù)資料
| 型號： | AD9956-VCO/PCBZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 16/32頁 |
| 文件大?。?/td> | 0K |
| 描述： | BOARD EVAL 14BIT 1.8V 48LFCSP |
| 產(chǎn)品培訓(xùn)模塊： | Direct Digital Synthesis Tutorial Series (1 of 7): Introduction Direct Digital Synthesizer Tutorial Series (7 of 7): DDS in Action Direct Digital Synthesis Tutorial Series (3 of 7): Angle to Amplitude Converter Direct Digital Synthesis Tutorial Series (6 of 7): SINC Envelope Correction Direct Digital Synthesis Tutorial Series (4 of 7): Digital-to-Analog Converter Direct Digital Synthesis Tutorial Series (2 of 7): The Accumulator |
| 標(biāo)準(zhǔn)包裝： | 1 |
| 系列： | AgileRF™ |
| 主要目的： | 計時，直接數(shù)字合成（DDS） |
| 已用 IC / 零件： | AD9956 |
| 已供物品： | 板 |
| 相關(guān)產(chǎn)品： | AD9956YCPZ-ND - IC SYNTHESIZER 1.8V 48LFCSP AD9956YCPZ-REEL7-ND - IC SYNTHESIZER 1.8V 48LFCSP |
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AD9956
Rev. A | Page 23 of 32
INSTRUCTION BYTE
The instruction byte contains the following information:
Table 4.
D7
D6
D5
D4
D3
D2
D1
D0
R/Wb
X
A4
A3
A2
A1
A0
R/Wb—Bit 7 of the instruction byte determines whether a read
or write data transfer occurs after the instruction byte write.
Logic 1 indicates a read operation. Logic 0 indicates a write
operation.
X, X—Bits 6 and 5 of the instruction byte are Don’t Care.
A4 to A0—Bits 4 to 0 of the instruction byte determine which
register is accessed during the data transfer portion of the
communications cycle.
SERIAL INTERFACE PORT PIN DESCRIPTION
SCLK—Serial Clock. The serial clock pin is used to synchronize
data to and from the AD9956 and to run the internal state
machines. The SCLK maximum frequency is 25 MHz.
CS—Chip Select Bar. CS is an active low input that allows more
than one device on the same serial communications line. The
SDO and SDI/O pins go to a high impedance state when this
input is high. If driven high during any communications cycle,
that cycle is suspended until CS is reactivated low. Chip select
can be tied low in systems that maintain control of SCLK.
SDI/O—Serial Data Input/Output. Data is always written to the
AD9956 on this pin. However, this pin can be used as a bidirec-
tional data line. CFR1<7> controls the configuration of this pin.
The default value (0) configures the SDI/O pin as bidirectional.
SDO—Serial Data Out. Data is read from this pin for protocols
that use separate lines for transmitting and receiving data. When
the AD9956 operates in a single bidirectional I/O mode, this pin
does not output data and is set to a high impedance state.
I/O_RESET—A high signal on this pin resets the I/O port state
machines without affecting the addressable registers’ contents.
An active high input on the I/O_RESET pin causes the current
communication cycle to abort. After I/O_RESET returns low
(0), another communication cycle can begin, starting with the
instruction byte write. Note that when not in use, this pin
should be forced low, because it floats to the threshold value.
MSB/LSB TRANSFERS
The AD9956 serial port can support both most significant bit
(MSB) first or least significant bit (LSB) first data formats. This
functionality is controlled by the LSB first bit in Control
Register 1 (CFR1<15>). The default value of this bit is low
(MSB first). When CFR1 <15> is set high, the AD9956 serial
port is in LSB first format. The instruction byte must be written
in the format indicated by CFR1 <15>. If the AD9956 is in LSB
first mode, the instruction byte must be written from least
significant bit to most significant bit. However, the instruction
byte phase of the communications cycle still precedes the data
transfer cycle.
For MSB first operation, all data written to (read from) the
AD9956 are in MSB first order. If the LSB mode is active, all
data written to (read from) the AD9956 are in LSB first order.
CS
SCLK
SDI/O
TPRE
TDSU
TSCLKW
TDHLD
SECOND BIT
FIRST BIT
SYMBOL
TPRE
TSCLKW
TDSU
TDHLD
MIN
6ns
40ns
6.5ns
0ns
DEFINITION
CS SETUP TIME
PERIOD OF SERIAL DATA CLOCK (WRITE)
SERIAL DATA SETUP TIME
SERIAL DATA HOLD TIME
04806-0-034
Figure 33. Timing Diagram for Data Write to AD9956
TDV
FIRST BIT
SECOND BIT
SDI/O
SDO
SCLK
CS
SYMBOL
TDV
TSCLKR
MAX
40ns
400ns
DEFINITION
DATA VALID TIME
PERIOD OF SERIAL DATA CLOCK (READ)
04806-0-035
TSCLKR
Figure 34. Timing Diagram for Data Read to AD9956
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9956XCPZ | 制造商:Analog Devices 功能描述:DGTL SYNTHESIZER 48LFCSP EP - Tape and Reel |
| AD9956YCP | 制造商:Analog Devices 功能描述:- Trays |
| AD9956YCPZ | 功能描述:IC SYNTHESIZER 1.8V 48LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9956YCPZ1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:2.7 GHz DDS-Based AgileRF |
| AD9956YCPZ-REEL1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:2.7 GHz DDS-Based AgileRF |
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