參數(shù)資料
型號(hào)： AD9925
廠商： Analog Devices, Inc.
英文描述： CCD Signal Processor with Vertical Driver and Precision Timing Generator
中文描述： CCD信號(hào)處理器垂直驅(qū)動(dòng)器和精密時(shí)序發(fā)生器
文件頁(yè)數(shù)： 42/96頁(yè)
文件大?。?/td> 1447K
代理商： AD9925
AD9925
Refer to Figure 51 for each step:
Rev. A | Page 42 of 96
1.
Write to the READOUT register (Addr x61) to specify the
number of fields to further suppress SUBCK while the
CCD data is readout. In this example, READOUT = 3.
Write to the EXPOSURE register (Addr x62) to specify the
number of fields to suppress SUBCK and VSG outputs dur-
ing exposure. In this example, EXPOSURE = 1.
Write to the TRIGGER register (Addr x60) to enable the
STROBE, MSHUT, and VSUB signals and to st
posure/readout operation. To trigger these events (as in
Figure 56), set the register TRIGGER = 31. Readout will
automatically occur after the exposure period is finished.
Write to the MODE register (x1B) to configure the next
five fields. The first two fie
same as the current draft mode fields, and the following
three fields are the still frame readout fields. The registers
for the draft mode field and the three readout fields have
already been programmed.
2.
The VD/HD falling edge will update the serial writes from 1.
3.
If VSUB mode = 0 (Addr x67), VSUB output will turn on at
the line specified in the VSUBON register (Addr x68).
4.
STROBE output turns on and off at the location specified
in the STROBEON and STROBEOFF registers (Addr x6E
to x71).
5.
MSHUT output turns off at the location specified in the
MSHUTOFF registers (Addr x6B and x6C).
6.
The next VD falling edge will automatically start the first
readout field.
7.
The next VD falling edge will automatically s art the sec-
ond readout field.
8.
The next VD falling edge will automatically start the third
readout field.
9.
Write to the MODE register to reconfigure the single draft
mode field timing. Write to the MSHUTON register
(Addr x6A) to open the mech
anical shutter.
10.
VD/HD falling edge will update the serial writes from 9.
VSG outputs return to draft mode timing.
SUBCK output resumes operation.
MSHUT output returns to the on position (active or open).
VSUB output returns to the off position (inactive).
art the ex-
lds during exposure are the
相關(guān)PDF資料
PDF描述
AD9925BBCZ CCD Signal Processor with Vertical Driver and Precision Timing Generator
AD9927 14-Bit CCD Signal Processor with V-Driver and Precision TimingTM Generator
AD9927BBCZ 14-Bit CCD Signal Processor with V-Driver and Precision TimingTM Generator
AD9927BBCZRL 14-Bit CCD Signal Processor with V-Driver and Precision TimingTM Generator
AD9929BBCZ CCD Signal Processor with Precision Timing Generator
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9925BBCZ 制造商:Analog Devices 功能描述:IC 12-BIT SIGNAL PROCESSOR
AD9925BBCZRL 制造商:Analog Devices 功能描述:IC 12-BIT SIGNAL PROCESSOR
AD9925KBCZ 制造商:Analog Devices 功能描述:12 BIT, 36 MSPS CCD SIGNAL PROCESSOR W/VERTICAL DRIVER - Bulk
AD9926BBCZ 制造商:Analog Devices 功能描述:
AD9926BBCZRL 制造商:Analog Devices 功能描述:
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*