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| 型號： | AD9925 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | CCD Signal Processor with Vertical Driver and Precision Timing Generator |
| 中文描述： | CCD信號處理器垂直驅(qū)動器和精密時序發(fā)生器 |
| 文件頁數(shù)： | 53/96頁 |
| 文件大?。?/td> | 1447K |
| 代理商： | AD9925 |
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AD9925
Table 33. Power-Up Register Write Sequence
Address
0x10
0x01
0x0A to 0x0D
TBD
0x00
0x04
0x7F
0x01
0x00 to 0xFF
TBD
Rev. A | Page 53 of 96
Data
De
Re
Standby V-Driver Input Signal Polarities
Power-Up the AFE and CLO Oscillator
Select Register Bank 2
VP
rtical Sequence, and Fi
Tim
ing
Select Register Bank 1
Reset Internal Timing Core
Ho
l and Shutter Timing
rizonta
Configure for Master Mode
Enable All Outputs after SYNC
SYNCPOL (for Software SYNC Only)
scription
set All
Registers to Default Va
lues
AT, Ve
eld
0x7F
0x15
0x31 to 0x71
0x20
0x11
0x13
0x00
0x01
TBD
0x01
0x01
0x01
Generating Software SYN
rnal SYNC pulse is
nternal SYNC in the AD9925 by writing to the SY
Addr 0x13). If the
ut (Pin J5) should
SYNC inp
out External SYNC
ailable, it is possible to
not av
L
re SYNC option is use
d to ground (VSS).
After power-up, follow the same procedure as before, for Steps 1
through 11. Then, for Step 12, instead of using the external
SYNC pulse, write a 1 to the SYNCPOL register. This will gen-
erate the SYNC internally, and the timing operation will begin.
SYNC during Master Mode Operation
he SYNC input may be used any time during operation to
resync the AD9925 counters with external timing, as shown in
Figure 68. The operation of the digital outputs may be suspended
during the SYNC operation by setting the SYNCSUSPEND regis-
ter (Addr 0x14) to a 1.
Power-Up and Synchronization in Slave Mode
The power-up procedure for slave mode operation is the same
as the procedure described for master mode operation, with
two exceptions:
1.
Eliminate Step 10. Do not write the part into master mode.
2.
No SYNC pulse is required in slave mode. Substitute Step
12 with starting the external VD and HD signals. This will
synchronize the part, allow the Bank 1 register updates,
and start the timing operation.
ode, the VD and HD in-
al counters. F
y of 23
he int
ure 69
t near
e reset o
aceme
of 18 pixe
.
re us
nize the intern
, there will be a latenc
lling edge of HD until t
eration is shown in Fig
eset op
oggle Position Plac
ional co
the ver
ters ar
tions sh
ollowing a
falling edg
(CLI) after
reset. The r
Vertical T
One addit
counters is
ternal coun
toggle posi
master clock edges
ernal H-Counter is
.
Counter Reset
f the internal
nt. Before the in-
ls where no
emen
nsideration during th
tical toggle position pl
e reset, there is an area
ould be programmed
For master
should not
SUBCK, H
the last 18 pixels befo
d for toggle position pl
BLK, or CLPOB puls
BLK, P
D falling edge
nt of the XV, XSG,
ure 70).
es (see Fig
Figure 71
restriction
and canno
delayed wi
ited area is
Additional Considerations for Toggle Positions
In addition to avoiding toggle position placement near the counter-
reset location, there are a couple of other recommendations.
he same example for sl
the last 18 pixels befo
ed. However, in slave m
ect to VD/HD placem
nt than it is in master
differe
de. The same
counters are reset
he counter reset is
erefore, the inhib-
mode.
Pixel location 0 should not be used for any of the toggle positions
for the XSG and SUBCK pulses.
Also, the propagation delay of the V-driver circuit should be con-
sidered when programming the toggle positions for the XV, XSG,
and SUBCK pulses. The delay of the V-driver circuit is specified
in Table 3 and is a maximum of 200 ns.
C with
Signal
gener-
NCPO
d, the
If an exte
ate an i
register (
softwa
be tie
T
When the AD9925 is used in slave m
puts a
ed to synchro
e of VD
the fa
mode,
be use
re the H
aceme
shows t
applies:
t be us
th resp
ave mo
re the
ode, t
ent; th
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