參數(shù)資料
型號(hào)： AD9911BCPZ-REEL7
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： 500 MSPS Direct Digital Synthesizer with 10-Bit DAC
中文描述： PARALLEL, WORD INPUT LOADING, 10-BIT DAC, QCC56
封裝： 8 X 8 MM, LEAD FREE, MO-220VLLD-2, LFCSP-56
文件頁(yè)數(shù)： 36/44頁(yè)
文件大?。?/td> 666K
代理商： AD9911BCPZ-REEL7
AD9911
CHANNEL REGISTER MAP
Table 25.
Register Name
(Address)
Channel
Function
1
(CFR)
(0x03)
Rev. 0 | Page 36 of 44
Bit
Range
<7:0>
Bit 7 (MSB)
Digital power-
down
Bit 6
DAC
power
down
Bit 5
Matched
pipe delays
active
Bit 4
Auto clear
sweep
accumulator
Bit 3
Clear sweep
accumulator
Bit 2
Auto clear
phase
accumulator
Bit 1
Clear phase
accumulator
2
(LSB)
Bit 0
Sine
wave
output
enable
Default
Value
0x02
<15:8>
Linear sweep
no-dwell
Linear
sweep
enable
Load SRR
at I/O
Update
Open
Open
Must be 0
DAC full-scale current
control <9:8>
0x03
<23:16>
Amplitude frequency
phase select <23:22>
Open <21:19>
Data align bits for SpurKiller mode
<18:16>
0x00
<7:0>
<15:8>
<23:16>
<31:24>
<7:0>
<15:8>
Frequency Tuning Word 0 <7:0>
Frequency Tuning Word 0 <15:8>
Frequency Tuning Word 0 <23:16>
Frequency Tuning Word 0 <31:24>
Phase Offset Word 0
0x00
0x00
0x00
Channel
Frequency Tuning
Word 0
1
(CTW0)
(0x04)
Channel Phase
1
Offset Word 0
(CPOW0) (0x05)
Amplitude
Control (ACR)
(0x06)
Open <15:14>
Phase Offset Word 0 <13:8>
<7:0>
<15:8>
Amplitude scale factor
Amplitude
multiplier
enable
Amplitude ramp rate <23:16>
Linear sweep rising ramp rate (RSRR) <7:0>
Linear sweep falling ramp rate (FSRR) <15:8>
0x00
0x00
Increment/decrement
step size <15:14>
Open
Ramp-up/
ramp-down
enable
Load ARR at I/O
update
Amplitude scale
factor <9:8>
<23:16>
<7:0>
<15:8>
–
–
–
Linear Sweep
Ramp Rate
1
(LSR)
(0x07)
LSR Rising Delta
1
(RDW) (0x08)
LSR Falling Delta
1
(FDW) (0x09)
1
There are four sets of channel registers and profile registers, one per channel. This is not shown in the channel or profile register maps because the addresses of all
channel registers and profile registers are the same for each channel. Therefore, the channel enable bits determine if the channel registers and/or profile registers are
written to or not.
2
The clear accumulator bit is set after a master reset. It self clears when an I/O update is asserted.
<7:0>
Rising delta word <7:0>
–
<15:8>
<23:16>
<31:24>
<7:0>
Rising delta word <15:8>
Rising delta word <23:16>
Rising delta word <31:24>
Falling delta word <7:0>
–
–
–
–
<15:8>
<23:16>
<31:24>
Falling delta word <15:8>
Falling delta word <23:16>
Falling delta word <31:24>
–
–
–
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