參數(shù)資料
型號(hào)： AD9911BCPZ-REEL7
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： 500 MSPS Direct Digital Synthesizer with 10-Bit DAC
中文描述： PARALLEL, WORD INPUT LOADING, 10-BIT DAC, QCC56
封裝： 8 X 8 MM, LEAD FREE, MO-220VLLD-2, LFCSP-56
文件頁(yè)數(shù)： 18/44頁(yè)
文件大小： 666K
代理商： AD9911BCPZ-REEL7
AD9911
THEORY OF OPERATION
PRIMARY DDS CORE
The AD9911 has one complete DDS (Channel 1) that consists
of a 32-bit phase accumulator, a phase-to-amplitude converter,
and 10-bit DAC. Together, these digital blocks generate a sine
wave when the phase accumulator is clocked and the phase
increment value (frequency tuning word) is greater than 0. The
phase-to-amplitude converter translates phase information to
amplitude information by a cos (θ) operation.
Rev. 0 | Page 18 of 44
The output frequency (f
O
) of the DDS is a function of the
rollover rate of the phase accumulator. The exact relationship is
shown in the following equation:
31
32
2
0
2
)
)(
(
≤
≤
=
FTW
with
f
FTW
f
S
O
where:
f
S
= the system clock rate.
FTW
= the frequency tuning word.
2
32
represents the capacity of the phase accumulator’.
The DDS core architecture also supports the capability to phase
offset the output signal. This is performed by the channel phase
offset word (CPOW). The CPOW is a 14-bit register that stores
a phase offset value. This value is added to the output of the
phase accumulator to offset the current phase of the output
signal. The exact value of phase offset is given by the following
equation:
°
×
=
Φ
360
2
14
CPOW
SPURKILLER/MULTITONE MODE AND TEST-TONE
MODULATION
The AD9911 is equipped with three auxiliary DDS cores
(Channel 0, Channel 2, and Channel 3). Because these channels
do not have a DAC, there is no direct output. Instead, these
channels are designed to implement either spur reduction/
multiple tones or test-tone modulation on the output spectrum
for Channel 1.
When using multitone mode, the device can output up to four
distinct carriers concurrently. This is possible via the summing
node for all four DDS cores. The frequency, phase and
amplitude of each tone is adjustable. The maximum amplitude
of the auxiliary channels is 12 db below the primary channel’s
maximum amplitude to prevent overdriving the DAC input.
The primary channel’s amplitude can be adjusted down to
achieve equal amplitude for all carriers.
When using SpurKiller mode, up to three spurs in the output
spectrum for Channel 1 are reducible (one per auxiliary
channel). To match an exact frequency using the three channels,
the spur must be harmonically related to the fundamental
frequency or the tuning word for Channel 1. A nonharmonic
spur may be impossible to match frequency.
Spur reduction is not as effective at lower fundamental
frequencies where SFDR performance is already very good. The
benefits of SpurKiller channels are virtually nonexistent when
the output frequency is less than 20% of the sampling
frequency.
Test-tone modulation is similar to amplitude modulation
options of a signal generator. For test-tone modulation,
auxiliary DDS Channel 0 is assigned to implement amplitude
sinusoidal modulated waveforms of the primary channel. This
function is programmed using internal registers.
D/A CONVERTER
The AD9911 incorporates a 10-bit current output DAC. The
DAC converts a digital code (amplitude) into a discrete analog
quantity. The DAC current outputs can be modeled as a current
source with high output impedance (typically 100 kΩ). Unlike
many DACs, these current outputs require termination into
AVDD via a resistor or a center-tapped transformer for
expected current flow.
The DAC has complementary outputs that provide a combined
full-scale output current (I
OUT
+ I
OUTB
). The outputs always sink
current.
The full-scale current is controlled by means of an external
resistor (R
SET
) and the scalable DAC current control bits
discussed in the Modes of Operation section. The Resistor R
SET
is connected between the DAC_RSET pin and analog ground
(AGND). The full-scale current is inversely proportional to the
resistor value as follows:
SET
OUT
R
I
91
.
18
=
Limiting the output to 10 mA with an R
SET
of 1.9 kΩ provides
optimal spurious-free dynamic range (SFDR) performance. The
DAC output voltage compliance range is AVDD + 0.5 V to
AVDD 0.5 V. Voltages developed beyond this range can cause
excessive harmonic distortion. Proper attention should be paid
to the load termination to keep the output voltage within its
compliance range. Exceeding this range could damage the DAC
output circuitry.
DAC
I
OUT
AVDD
1:1
50
I
OUT
0
LPF
Figure 35. Typical DAC Output Termination Configuration
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9912 制造商:AD 制造商全稱:Analog Devices 功能描述:1 GSPS Direct Digital Synthesizer w/ 14-bit DAC
AD9912/PCBZ 制造商:Analog Devices 功能描述:Evaluation Kit For 1 GSPS Direct Digital Synthesizer W/ 14-Bit DAC 制造商:Analog Devices 功能描述:EVAL KIT FOR 1 GSPS DIRECT DGTL SYNTHESIZER W/ 14BIT DAC - Bulk 制造商:Analog Devices 功能描述:EVALUATION BOARD AD9912 1GSPS DDS
AD9912A/PCBZ 功能描述:BOARD EVALUATION FOR AD9912 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評(píng)估演示板和套件 系列:- 標(biāo)準(zhǔn)包裝:1 系列:PCI Express® (PCIe) 主要目的:接口，收發(fā)器，PCI Express 嵌入式:- 已用 IC / 零件:DS80PCI800 主要屬性:- 次要屬性:- 已供物品:板
AD9912ABCPZ 功能描述:IC DDS 1GSPS DAC 14BIT 64LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
AD9912ABCPZ-REEL7 功能描述:IC DDS 1GSPS DAC 14BIT 64LFCSP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
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