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參數(shù)資料
| 型號： | AD9887 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Dual Interface for Flat Panel Displays |
| 中文描述： | 雙接口的平板顯示器 |
| 文件頁數(shù)： | 16/40頁 |
| 文件大?。?/td> | 321K |
| 代理商： | AD9887 |
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REV. 0
–16–
AD9887
Table V. VCO Frequency Ranges
Pixel Clock
Range (MHz)
K
VCO
Gain
(MHz/V)
PV1
PV0
0
0
1
1
0
1
0
1
12–35
35–70
70–110
110–140
150
150
150
180
Table VI. Charge Pump Current/Control Bits
Ip2
Ip1
Ip0
Current ( A)
0
0
0
0
1
1
1
1
0
0
1
1
0
0
1
1
0
1
0
1
0
1
0
1
50
100
150
250
350
500
750
1500
3. The 3-Bit Charge Pump Current Register. This register
allows the current that drives the low pass loop filter to be
varied. The possible current values are listed in Table VI.
provides 32 phase-shift steps of 11.25
°
each. The Hsync
signal with an identical phase shift is available through the
HSOUT pin. Phase adjustment is still available if the pixel
clock is being provided externally.
4. The 5-Bit Phase Adjust Register. The phase of the generated
sampling clock may be shifted to locate an optimum sam-
pling point within a clock cycle. The Phase Adjust register
The COAST allows the PLL to continue to run at the same
frequency, in the absence of the incoming Hsync signal. This
may be used during the vertical sync period, or any other
time that the Hsync signal is unavailable. The polarity of
the COAST signal may be set through the Coast Polarity Bit.
Also, the polarity of the Hsync signal may be set through the
HSYNC polarity Bit. If not using automatic polarity
detection, the HSYNC and COAST polarity bits should
be set to match the Polarity of their respective signals.
Table VII. Recommended VCO Range and Charge Pump Current Settings for Standard Display Formats
Horizontal
Frequency
(kHz)
Refresh
Rate (Hz)
Pixel Rate
(MHz)
Standard
Resolution
640
×
480
VCORNGE
CURRENT
VGA
60
72
75
85
31.5
37.7
37.5
43.3
25.175
31.500
31.500
36.000
00
00
00
00
101
101
110
110
SVGA
800
×
600
56
60
72
75
85
35.1
37.9
48.1
46.9
53.7
36.000
40.000
50.000
49.500
56.250
00
01
01
01
01
101
101
101
101
110
XGA
1024
×
768
60
70
75
80
85
48.4
56.5
60.0
64.0
68.3
65.000
75.000
78.750
85.500
94.500
01
10
10
10
10
110
101
101
101
101
SXGA
1280
×
1024
60
75
85
64.0
80.0
91.1
108.000
135.000
157.500
*
10
11
10
110
110
110
UXGA
1600
×
1200
60
65
70
75
85
75.0
81.3
87.5
93.8
106.3
162.000
*
175.500
*
189.000
*
202.500
*
229.500
*
10
10
10
10
11
110
110
110
110
110
*
Graphics sampled at one-half the incoming pixel rate using Alternate Pixel Sampling mode.
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| AD9888 | 100/140/170/205 MSPS Analog Flat Panel Interface |
| AD9888KS-100 | 100/140/170/205 MSPS Analog Flat Panel Interface |
| AD9888KS-140 | TRI N PLUG F 2-13 |
| AD9888KS-170 | TRI N RECP M FLG 2-13 |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9887/PCB | 制造商:Analog Devices 功能描述:INTRFC DUAL FOR FLAT PNL DISPLAYS 160MQFP - Bulk |
| AD9887A | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual Interface for Flat Panel Displays |
| AD9887A/PCB | 制造商:Analog Devices 功能描述:INTRFC FOR FLAT PNL DISPLAY 16SOIC W - Bulk |
| AD9887AKS-100 | 制造商:Analog Devices 功能描述:Interface for Flat Panel Display 160-Pin MQFP 制造商:Rochester Electronics LLC 功能描述:DUAL A/D INTERFACE FOR FLAT PANEL - Bulk |
| AD9887AKS-140 | 制造商:Rochester Electronics LLC 功能描述:DUAL A/D INTERFACE FOR FLAT PANEL - Bulk 制造商:Analog Devices 功能描述: |
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