參數(shù)資料
型號(hào)： AD9856AST
廠商： ANALOG DEVICES INC
元件分類： 通信及網(wǎng)絡(luò)
英文描述： CMOS 200 MHz Quadrature Digital Upconverter
中文描述： SPECIALTY TELECOM CIRCUIT, PQFP48
封裝： LQFP-48
文件頁(yè)數(shù)： 5/32頁(yè)
文件大小： 429K
代理商： AD9856AST
AD9856
–5–
REV. B
FUNCTIONAL BLOCK AND MODE DESCRIPTION
Operating Modes
1. Complex quadrature modulator mode.
2. Single tone output mode.
Programmable: 12-bit, 6-bit, or 3-bit input formats. Data input to the AD9856 is
12-bit, twos complement. Complex I/Q symbol component data is required to be at
least 2
×
oversampled, depending upon configuration.
Up to 50 Msamples/s @ 200 MHz SYSCLK rate.
For DC-80 MHz A
OUT
operation (200 MHz SYSCLK rate):
w/REFCLK Multiplier enabled: 10 MHz–50 MHz, programmable via control bus
w/REFCLK Multiplier disabled: 200 MHz.
Note: For optimum data synchronization, the AD9856 Reference Clock, and the
input data clock, should be derived from the same clock source.
Programmable in integer steps over the range of 4
×
–20
×
. Can be disabled (effective
REFCLK Multiplier = 1) via control bus. Output of REFCLK Multiplier = SYSCLK
rate, which is the internal clock rate applied to the DDS and DAC function.
Four pin-selectable, preprogrammed formats. Available for modulation and single
tone operating modes.
Fixed 4
×
, selectable 2
×
and selectable 2
×
–63
×
range
.
Interpolating filters that provide upsampling and reduce the effects of the CIC
passband roll-off characteristics.
When Burst Mode is enabled via the control bus, the rising edge of the applied
TxENABLE pulse should be coincident with, and frame, the input data packet. This
establishes data sampling synchronization.
When continuous mode is enabled via the control bus, the TxENABLE pin becomes
an I/Q control line. A Logic “1” on TxENABLE indicates I data is being presented
to the AD9856. A Logic “0” on TxENABLE indicates Q data is being presented to the
AD9856. Each rising edge of TxENABLE resynchronizes the AD9856 input sam-
pling capability.
Precompensates for SIN(x)/x roll-off of DAC; user bypassable.
[I
×
Cos(
ω
t) + Q
×
Sin(
ω
t)] or [I
×
Cos(
ω
t) – Q
×
Sin(
ω
t)] (default), configurable via
control bus, per profile.
Power dissipation reduced to less than 6 mW when Full Sleep Mode active, program-
mable via control bus.
Input Data Format
Input Sample Rate
Input Reference Clock Frequency
Internal Reference Clock Multiplier
Profile Select
Interpolating Range
Half-Band Filters
TxENABLE Function–Burst Mode
TxENABLE Function–Continuous Mode
Inverse SINC Filter
I/Q Channel Invert
Full Sleep Mode
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