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參數(shù)資料
| 型號： | AD9856AST |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | 通信及網(wǎng)絡 |
| 英文描述： | CMOS 200 MHz Quadrature Digital Upconverter |
| 中文描述： | SPECIALTY TELECOM CIRCUIT, PQFP48 |
| 封裝： | LQFP-48 |
| 文件頁數(shù)： | 25/32頁 |
| 文件大小： | 429K |
| 代理商： | AD9856AST |
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AD9856
–25–
REV. B
R/
W
–Bit 7 of the instruction byte determines whether a read or
write data transfer will occur after the instruction byte write.
Logic high indicates read operation. Logic zero indicates a write
operation.
N1, N0—Bits 6 and 5 of the instruction byte determine the
number of bytes to be transferred during the data transfer cycle
of the communications cycle. The bit decodes are shown in
Table IV.
Table IV. N1, N2 Decode Bits
N1
N0
Description
0
0
1
1
0
1
0
1
Transfer 1 Byte
Transfer 2 Bytes
Transfer 3 Bytes
Transfer 4 Bytes
A4, A3, A2, A1, A0—Bits 4, 3, 2, 1, 0 of the instruction byte
determine which register is accessed during the data transfer
portion of the communications cycle. For multibyte transfers,
this address is the starting byte address. The remaining register
addresses are generated by the AD9856.
SERIAL INTERFACE PORT PIN DESCRIPTION
SCLK—Serial Clock. The serial clock pin is used to synchronize
data to and from the AD9856 and to run the internal state ma-
chines. SCLK maximum frequency is 10 MHz.
CS
—Chip Select. Active low input that allows more than one
device on the same serial communications lines. The SDO and
SDIO pins will go to a high impedance state when this input is
high. If driven high during any communications cycle, that cycle
is suspended until
CS
is reactivated low. Chip Select can be tied
low in systems that maintain control of SCLK.
SDIO—Serial Data I/O. Data is always written into the AD9856
on this pin. However, this pin can be used as a bidirectional
data line. The configuration of this pin is controlled by Bit 7 of
register address 0h. The default is logic zero, which configures
the SDIO pin as bidirectional.
SDO—Serial Data Out. Data is read from this pin for protocols
that use separate lines for transmitting and receiving data. In the
case where the AD9856 operates in a single bidirectional I/O
mode, this pin does not output data and is set to a high imped-
ance state.
SYNC I/O—Synchronizes the I/O port state machines without
affecting the addressable registers contents. An active high input
on the SYNC I/O pin causes the current communication cycle
to abort. After SYNC I/O returns low (Logic 0) another com-
munication cycle may begin, starting with the instruction byte
write.
CA CLK—Output clock pin to the AD8320/AD8321. If using
the AD9856 to control the AD8320/AD8321 Programmable
Cable Driver Amplifier, connect this pin to the CLK input of
the AD8320/AD8321.
CA DATA—Output data pin to the AD8320/AD8321. If using
the AD9856 to control the AD8320/AD8321 Programmable
Cable Driver Amplifier, connect this pin to the SDATA input of
the AD8320/AD8321.
CA ENABLE—Output Enable pin to the AD8320/AD8321. If
using the AD9856 to control the AD8320/AD8321 Program-
mable Cable Driver Amplifier, connect this pin to the DATAEN
input of the AD8320/AD8321.
MSB/LSB TRANSFERS
The AD9856 serial port can support both most significant bit
(MSB) first or least significant bit (LSB) first data formats. This
functionality is controlled by the REG0<6> bit. The default value
of REG0<6> is low (MSB first). When REG0<6> is set active
high, the AD9856 serial port is in LSB first format. The instruc-
tion byte must be written in the format indicated by REG0<6>.
That is, if the AD9856 is in LSB first mode, the instruction byte
must be written from least significant bit to most significant bit.
Multibyte data transfers in MSB format can be completed by
writing an instruction byte that includes the register address
of the most significant byte. In MSB first mode, the serial port
internal byte address generator decrements for each byte
required of the multibyte communication cycle. Multibyte data
transfers in LSB first format can be completed by writing an
instruction byte that includes the register address of the least
significant byte. In LSB first
mode, the serial port internal byte
address generator increments for each byte required of the
multibyte communication cycle.
NOTES ON SERIAL PORT OPERATION
The AD9856 serial port configuration bits reside in Bits 6 and 7
of register address 0h. It is important to note that the configura-
tion changes
immediately
upon writing to this register. For
multibyte transfers, writing to this register may occur during the
middle of a communication cycle. Care must be taken to
compensate for this new configuration for the remainder of
the current communication cycle.
The AD9856 serial port controller address can roll from 19h to
0h for multibyte I/O operations if the MSB first mode is active.
The serial port controller address can roll from 0h to 19h for
multibyte I/O operations if the LSB first mode is active.
The system must maintain synchronization with the AD9856 or
the internal control logic will not be able to recognize further
instructions. For example, if the system sends an instruction
byte for a 2-byte write, then pulses the SCLK pin for a 3-byte
write (24 additional SCLK rising edges), communication syn-
chronization is lost. In this case, the first 16 SCLK rising edges
after the instruction cycle will properly write the first two data
bytes into the AD9856, but the next eight rising SCLK edges
are interpreted as the next instruction byte,
not
the final byte of
the previous communication cycle.
In the case where synchronization is lost between the system
and the AD9856, the SYNC I/O pin provides a means to re-
establish synchronization without re-initializing the entire chip.
The SYNC I/O pin enables the user to reset the AD9856 state
machine to accept the next eight SCLK rising edges to be coin-
cident with the instruction phase of a new communication cycle.
By applying and removing a “high” signal to the SYNC I/O pin,
the AD9856 is set to once again begin performing the commu-
nication cycle in synchronization with the system. Any informa-
tion that had been written to the AD9856 registers during a
valid communication cycle prior to loss of synchronization will
remain intact.
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相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9856ASTZ | 功能描述:IC UPCONVERTER DGTL QUAD 48TQFP RoHS:是 類別:RF/IF 和 RFID >> RF 其它 IC 和模塊 系列:AD9856 標準包裝:100 系列:* |
| AD9857 | 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS 200 MSPS 14-Bit Quadrature Digital Upconverter |
| AD9857/PCB | 制造商:Analog Devices 功能描述:Evaluation Board For AD9857 |
| AD9857/PCBZ | 功能描述:BOARD EVALUATION FOR AD9857 RoHS:是 類別:RF/IF 和 RFID >> RF 評估和開發(fā)套件，板 系列:- 標準包裝:1 系列:- 類型:GPS 接收器 頻率:1575MHz 適用于相關產(chǎn)品:- 已供物品:模塊 其它名稱:SER3796 |
| AD9857/PCBZ | 制造商:Analog Devices 功能描述:EVAL BOARD, AD9857 DIRECT DIGITAL SYNTHE |
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