參數(shù)資料
型號: AD9856AST
廠商: ANALOG DEVICES INC
元件分類: 通信及網(wǎng)絡
英文描述: CMOS 200 MHz Quadrature Digital Upconverter
中文描述: SPECIALTY TELECOM CIRCUIT, PQFP48
封裝: LQFP-48
文件頁數(shù): 15/32頁
文件大?。?/td> 429K
代理商: AD9856AST
AD9856
–15–
REV. B
Figure 24 describes the input timing for half word mode, burst
input timing operation.
In half word mode, data is input on the D<11:6> inputs. The
D<5:0> inputs are unused in this mode and should be tied to
DGND or DVDD. The AD9856 expects the data to be input in
the following manner: I<11:6>,I<5:0>,Q<11:6>,Q<5:0>.
Data is twos complement, the sign bit is D<11> in notation
I<11:0>,Q<11:0>.
The input sample rate for half word mode, when the third half-
band filter is engaged, is given by:
f
IN
=
SYSCLK
/2
N
where
N
is the CIC interpolation rate.
The input sample rate for half word mode, when the third half-
band filter is not engaged is given by:
f
IN
=
SYSCLK
/
N
where
N
is the CIC interpolation rate.
Figure 25 describes the input timing for quarter word, burst
input timing operation.
In quarter word mode, data is input on the D<11:9> inputs.
The D<8:0> inputs are unused in this mode and should be tied
to DGND or DVDD. The AD9856 expects the data to be input
in the following manner: I<11:9>, I<8:6>, I<5:3>, I<2:0>,
Q<11:9>, Q<8:6>, Q<5:3>, Q<2:0>. Data is twos comple-
ment, the sign bit is D<11> in notation I<11:0>, Q<11:0>.
The input sample rate for quarter word mode, when the third
half-band filter is engaged, is given by:
f
IN
=
SYSCLK/N
where
N
is the CIC interpolation rate.
Please note that Half-Band Filter #3 must be engaged when operat-
ing in quarter word mode.
TxENABLE
D(11:0)
INTERNAL I
INTERNAL Q
I0
Q0
I1
Q1
I2
Q2
I3
Q3
I4
Q4
I0
I1
I2
I3
Q0
Q1
Q2
Q3
Figure 22. 12-Bit Input Mode, Classic Burst Timing
TxENABLE
D(11:0)
INTERNAL I
INTERNAL Q
I0
Q0
I1
Q1
I2
Q2
I3
Q3
I4
Q4
I0
I1
I2
I3
Q0
Q1
Q2
Q3
Figure 23. 12-Bit Input Mode, Alternate TxENABLE Timing
TxENABLE
D(11:6)
INTERNAL I
INTERNAL Q
I0
I1
Q0
Q1
I0(11:6)
I0(5:0)
Q0(5:0)
I1(11:6)
I1(5:0)
Q1(11:6)
Q1(5:0)
I2(11:6)
Q0(11:6)
I2(5:0)
Figure 24. 6-Bit Input Mode, Burst Mode Timing
I0(11:9)
I0(8:6)
I0(5:3)
I0(2:0)
Q0(11:9)
Q0(8:6)
Q0(5:3)
Q0(2:0)
I1(11:9)
I1(8:6)
TxENABLE
D(11:9)
INTERNAL I
INTERNAL Q
I0
Q0
Figure 25. 3-Bit Input Mode, Burst Mode Timing
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AD9856 CMOS 180 MHz Quadrature Digital Upconverter(時鐘頻率為180MHz,CMOS的積分上變頻器)
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