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參數(shù)資料
| 型號： | AD9854ASQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | XO, clock |
| 英文描述： | CMOS 300 MHz Quadrature Complete-DDS |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 30 MHz, PQFP80 |
| 封裝： | MS-026-BEC, LQFP-80 |
| 文件頁數(shù)： | 35/44頁 |
| 文件大?。?/td> | 433K |
| 代理商： | AD9854ASQ |
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AD9854
–35–
REV. 0
EVALUATION BOARD
An evaluation board is available that supports the AD9854 DDS
devices. This evaluation board consists of a PCB, software, and
documentation to facilitate bench analysis of the performance of
the AD9854 device. It is recommended that users of the AD9854
familiarize themselves with the operation and performance
capabilities of the device with the evaluation board. The evaluation
board should also be used as a PCB reference design to ensure
optimum dynamic performance from the device.
OPERATING INSTRUCTIONS
To assist in proper placement of the pin-header shorting-jumpers,
the instructions will refer to direction (left, right, top, bottom)
as well as header pins to be shorted. Pin #1 for each three pin-
header has been marked on the PCB corresponding with the
schematic diagram. When following these instructions, position
the PCB so that the text can be read from left to right. The
board is shipped with the pin-headers configuring the board
as follows:
1. REFCLK for the AD9854 is configured as differential. The
differential clock signals are provided by the 100LVEL16
differential receiver.
2. Input clock for the 100LVEL16 is single-ended via J5. This
signal may be 3.3 V CMOS or a 2 V p-p sine wave capable of
driving 50
(R8).
3. Both DAC outputs from the AD9854 are routed through
the two 120 MHz elliptical LP filters and their outputs con-
nected to J3 (Q) and J4 (I).
4. The board is set up for software control via the printer port
connector.
5. Configured for AD9854 operation.
Load the software
from the CD onto the host PC’s hard disk.
Only Windows 9X and NT operating system are supported.
Connect a printer cable from the PC to the AD9854 Evaluation
Board printer port connector labeled “J11.”
Attach power
wires to connector labeled “TB1” using the screw-
down terminals. This is a plastic connector that press-fits over a
4-pin header soldered to the board. Table IX below shows con-
nections to each pin. DUT = “device under test.”
Table IX. Power Requirements for DUT Pins
AVDD 3.3 V
for All DUT
Analog Pins
DVDD 3.3 V
for All DUT
Digital Pins
VCC 3.3 V
for All Other
Devices
Ground
—for All
Devices
Attach REFCLK
There are three possibilities to choose from:
1. On-Board (But Optional) Crystal Clock Oscillator, Y1.
Insert an appropriate 3.3 V CMOS clock oscillator. See that
the shorting jumper at W5 is located on Pins 1 and 2 (the left
two pins). This routes the single-ended oscillator output to a
very high speed “Differential Receiver” (the MC100LVEL16),
where the signal is transformed to a
differential PECL output
.
To route the differential output signals to AD9854, two more
switches must be configured. W9
must have a shorting jumper
on Pins 2 and 3 (the right two pins). To engage the differen-
tial clocking mode of the AD9854 W3
,
Pins 2 and 3 (the right
two pins) must be connected with a shorting jumper.
2. External Differential Clock Input, J5.
This is actually just another single-ended input that will be
routed to the MC100LVEL16 for conversion to differential
PECL output. This is accomplished by attaching a 2 V p-p
clock or sine wave source to J5. Note that this is a 50
impedance point set by R8. The input signal will be ac-coupled
and then biased to the center switching threshold of the
MC100LVEL16. Position the shorting jumper of W5
to Pins
2 and 3 (the right two pins) to route the signal at J5 to the
differential receiver IC. To route the differential output signals
to AD9854, two more switches must be configured. W9
must
have a shorting jumper on Pins 2 and 3 (the right two pins).
To engage the differential clocking mode of the AD9854
W3
,
Pins 2 and 3 (the right two pins) must be connected
with a shorting jumper.
3. External Single-Ended Clock Input, J7
.
This mode bypasses the MC100LVEL16 and directly drives
the AD9854 with your reference clock. Attach a 50
, 2 V p-p
sine source that is dc offset to 1.65 V, or a 50
CMOS-level
clock source to J7. Remove the shorting jumper from W5
altogether to make certain that the device (U3) Is not Toggling
or Self-Oscillating. Set the shorting jumper at W9
on Pins
1 and 2 (the left two pins) to route the REFCLK signal from
J7 to Pin 69 of the AD9854. Finally, set the shorting jumper at
W3 to Pins 1 and 2 (the left two pins) to place the AD9854 in
the single-ended clock mode.
Regardless of the origination, the signals arriving at the AD9854
are called the Reference Clock. If you choose to engage the
on-chip REFCLK Multiplier, this signal is the reference clock
for the REFCLK Multiplier and the REFCLK Multiplier output
becomes the
SYSTEM CLOCK. If you choose to bypass the
REFCLK Multiplier, the reference clock that you have supplied
is directly operating the AD9854 and is, therefore, the system
clock.
Three-state control or switch headers W11, W12, W14, and
W15 must be shorted to allow the provided software to control
the AD9854 evaluation board via the printer port connector J11.
If programming of the AD9854 is not to be provided by the host
PC via the ADI software, then headers W11, W12, W14, and W15
should be opened (shorting jumpers removed). This effectively
detaches the PC interface and allows the 40-pin header, J10, to
assume control without bus contention. Input signals on J10 going
to the AD9854 should be 3.3 V CMOS logic levels.
Low-Pass Filter Testing
The purpose of 2-pin headers W7 and W10 (associated with J1
and J2) are to allow the two 50
, 120 MHz filters to be tested
during PCB assembly without interference from other circuitry
attached to the filter inputs.
Normally, a shorting jumper will be
attached to each header to allow the DAC signals to be routed to the
filters.
If the user wishes to test the filters, the shorting jumpers
at W7 and W10 should be removed and 50
test signals applied
at J1 and J2 inputs to the 50
elliptic filters. User should refer
to Figure 62 and the following sections to properly position the
remaining shorting jumpers.
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9854AST | CMOS 300 MHz Quadrature Complete-DDS |
| AD9856AST | CMOS 200 MHz Quadrature Digital Upconverter |
| AD9856 | CMOS 180 MHz Quadrature Digital Upconverter(時鐘頻率為180MHz,CMOS的積分上變頻器) |
| AD9857 | CMOS 200 MSPS 14-Bit Quadrature Digital Upconverter |
| AD9857AST | CMOS 200 MSPS 14-Bit Quadrature Digital Upconverter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9854ASQZ | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 300MHz 2-DAC 12-Bit Parallel/Serial 80-Pin LQFP 制造商:Analog Devices 功能描述:Communication IC |
| AD9854AST | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 300MHz 2-DAC 12-Bit Parallel/Serial 80-Pin LQFP Tray 制造商:Rochester Electronics LLC 功能描述:200 MHZ QUADRATURE DDS SYNTHESIZER - Tape and Reel 制造商:Analog Devices 功能描述:IC SEMICONDUCTOR ((NS)) |
| AD9854ASTZ | 功能描述:IC DDS QUADRATURE CMOS 80-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標準包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9854ASVZ | 制造商:Analog Devices 功能描述:CMOS 300 MSPS QUADRATURE COMPLETE DDS 制造商:Analog Devices 功能描述:CMOS 300 MSPS QUADRATURE COMPLETE DDS - Trays 制造商:Analog Devices 功能描述:SYNTHESIZER 制造商:Analog Devices 功能描述:Complete DDS Quadrature 300MSPS TQFP80 |
| AD9854PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS 300 MSPS Quadrature Complete DDS |
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