參數(shù)資料
型號(hào)： AD9854ASQ
廠商： ANALOG DEVICES INC
元件分類： XO, clock
英文描述： CMOS 300 MHz Quadrature Complete-DDS
中文描述： PLL FREQUENCY SYNTHESIZER, 30 MHz, PQFP80
封裝： MS-026-BEC, LQFP-80
文件頁(yè)數(shù)： 15/44頁(yè)
文件大?。?/td> 433K
代理商： AD9854ASQ
AD9854
–15–
REV. 0
Next, the transition time from zero-scale to full-scale must
be programmed. The transition time is a function of two fixed
elements and one variable. The variable element is the program-
mable 8-bit RAMP RATE COUNTER
.
This is a down-counter
being clocked at the system clock rate (300 MHz max) that out-
puts one pulse whenever the counter reaches zero. This pulse is
routed to a 12-bit counter that increments one LSB for every
pulse received. The outputs of the 12-bit counter are connected
to the 12-bit digital multiplier. When the digital multiplier has a
value of all zeros at its inputs, the input signal is multiplied
by zero, producing zero-scale. When the multiplier has a value
of all ones, the input signal is multiplied by a value of one, pro-
ducing full-scale. There are 4094 remaining fractional multiplier
values that will produce output amplitudes corresponding to
their binary values.
The two fixed elements are the clock period of the system clock,
which drives the Ramp Rate Counter, and the 4096 amplitude
steps between zero-scale and full-scale. To give an example,
assume that the System Clock of the AD9854 is 100 MHz (10ns
period). If the Ramp Rate Counter is programmed for a minimum
count of five, it will take two system clock periods (one rising
edge loads the count-down value, the next edge decrements the
counter from five to four). The relationship of the 8-bit count-
down value to the time period between output pulses is given as:
(N+1)
×
SYSTEM CLOCK PERIOD
,
where
N
is the 8-bit count-down value. It will take 4096 of these
pulses to advance the 12-bit up-counter from zero-scale to full-
scale. Therefore, the minimum shaped keying ramp time for a
100 MHz system clock is 4096
×
6
×
10 ns = approximately 246
μ
s.
The maximum ramp time will be 4096
×
256
×
10 ns = approxi-
mately 10.5
μ
s.
Finally, changing the logic state of Pin 30, “shaped keying” will
automatically perform the programmed output envelope functions
when OSK INT is high. A logic high on Pin 30 causes the out-
puts to linearly ramp up to full-scale amplitude and hold until
the logic level is changed to low, causing the outputs to ramp
down to zero-scale.
I and Q DACs
The 300 MSPS (maximum) sine and cosine wave outputs of the
DDS. Their maximum output amplitudes are set by the DAC
R
SET
resistor at Pin 56. These are current-out DACs with a
full-scale maximum output of 20 mA; however, a nominal 10 mA
12-BIT DIGITAL
MULTIPLIER
12
12
(BYPASS MULTIPLIER)
OSK EN = 0
OSK EN = 1
OSK EN = 0
OSK EN = 1
12
12
DIGITAL
SIGNAL IN
USER PROGRAMMABLE
12-BIT Q-CHANNEL
MULTIPLIER
"OUTPUT SHAPE
KEY Q MULT"
REGISTER
12
OSK EN = 1
OSK EN = 0
1
8-BIT DOWN-
COUNTER
SYSTEM
CLOCK
SHAPING
KEYING PIN
SINE DAC
12-BIT
COUNTER
Figure 32. Block diagram of Q-pathway of the digital multiplier section responsible for Shaped Keying function.
The I-pathway is similar, except that no alternate 12-bit Q-DAC source register is provided.
output current provides best spurious-free dynamic range (SFDR)
performance. The value of R
SET
= 39.93/I
OUT
, where I
OUT
is in
amps. DAC output compliance specification limits the maximum
voltage developed at the outputs to –0.5 V to +1 V. Voltages
developed beyond this limitation will cause excessive DAC
distortion and possibly permanent damage. The user must choose
a proper load impedance to limit the output voltage swing to
the compliance limits. Both DAC outputs should be terminated
equally for best SFDR, especially at higher output frequencies
where harmonic distortion errors are more prominent.
Both DACs are preceded by inverse SIN(x)/x filters (a.k.a. inverse
sinc filters) that precompensate for DAC output amplitude varia-
tions over frequency to achieve flat amplitude response from dc
to Nyquist. Digital multipliers follow the inverse sinc filters to
allow amplitude control, amplitude modulation and amplitude
shaped keying. The inverse sinc filters (address 20 hex, Bypass
Inv Sinc
bit)) and digital multipliers (address 20 hex, OSK EN
bit) can be bypassed for power conservation by setting those bits
high. Both DACs can be powered down by setting the DAC PD
bit high (address 1D of control register) when not needed.
I-DAC outputs are designated as IOUT1 and IOUT1B, Pins
48 and 49 respectively. Q-DAC outputs are designated as IOUT2
AND IOUT2B, Pins 52 and 51 respectively.
Control DAC
The 12-bit Q DAC can be reconfigured to perform as a “control”
or auxiliary DAC. The control DAC output can provide dc
control levels to external circuitry, generate ac signals, or enable
duty cycle control of the on-board comparator. When the SRC
QDAC bit in control register (parallel address 1F hex) is set
high, the Q DAC inputs are switched from internal 12-bit Q
data source (default setting) to external 12-bit
,
twos-complement
data, supplied by the user. Data is channeled through the serial or
parallel interface to the 12-bit Q DAC register (address 26 and 27
hex) at a maximum 100 MHz data rate. This DAC is clocked at
the system clock, 300 MSPS (maximum), and has the same maxi-
mum output current capability as that of the I DAC. The single
R
SET
resistor on the AD9854 sets the full-scale output current
for both DACs. The control DAC can be separately powered
down for power conservation when not needed by setting the
Q DAC POWER-DOWN bit high (address 1D hex). Control
DAC outputs are designated as IOUT2 and IOUT2B (Pins 52
and 51 respectively).
相關(guān)PDF資料
PDF描述
AD9854AST CMOS 300 MHz Quadrature Complete-DDS
AD9856AST CMOS 200 MHz Quadrature Digital Upconverter
AD9856 CMOS 180 MHz Quadrature Digital Upconverter(時(shí)鐘頻率為180MHz,CMOS的積分上變頻器)
AD9857 CMOS 200 MSPS 14-Bit Quadrature Digital Upconverter
AD9857AST CMOS 200 MSPS 14-Bit Quadrature Digital Upconverter
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9854ASQZ 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 300MHz 2-DAC 12-Bit Parallel/Serial 80-Pin LQFP 制造商:Analog Devices 功能描述:Communication IC
AD9854AST 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 300MHz 2-DAC 12-Bit Parallel/Serial 80-Pin LQFP Tray 制造商:Rochester Electronics LLC 功能描述:200 MHZ QUADRATURE DDS SYNTHESIZER - Tape and Reel 制造商:Analog Devices 功能描述:IC SEMICONDUCTOR ((NS))
AD9854ASTZ 功能描述:IC DDS QUADRATURE CMOS 80-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR)
AD9854ASVZ 制造商:Analog Devices 功能描述:CMOS 300 MSPS QUADRATURE COMPLETE DDS 制造商:Analog Devices 功能描述:CMOS 300 MSPS QUADRATURE COMPLETE DDS - Trays 制造商:Analog Devices 功能描述:SYNTHESIZER 制造商:Analog Devices 功能描述:Complete DDS Quadrature 300MSPS TQFP80
AD9854PCB 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS 300 MSPS Quadrature Complete DDS
發(fā)布緊急采購(gòu)，3分鐘左右您將得到回復(fù)。

采購(gòu)需求

(若只采購(gòu)一條型號(hào)，填寫一行即可)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

發(fā)布成功！您可以繼續(xù)發(fā)布采購(gòu)。也可以進(jìn)入我的后臺(tái)，查看報(bào)價(jià)

*型號(hào) *數(shù)量 廠商 批號(hào) 封裝
添加更多采購(gòu)

我的聯(lián)系方式

*
*
*