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參數(shù)資料
| 型號： | AD9854ASQ |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | XO, clock |
| 英文描述： | CMOS 300 MHz Quadrature Complete-DDS |
| 中文描述： | PLL FREQUENCY SYNTHESIZER, 30 MHz, PQFP80 |
| 封裝： | MS-026-BEC, LQFP-80 |
| 文件頁數(shù)： | 28/44頁 |
| 文件大?。?/td> | 433K |
| 代理商： | AD9854ASQ |
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AD9854
–28–
REV. 0
Serial Port I/O Operation
With the S/P SELECT pin tied low, the serial I/O mode is active.
The AD9854 serial port is a flexible, synchronous, serial com-
munications port allowing easy interface to many industry-standard
microcontrollers and microprocessors. The serial I/O is compat-
ible with most synchronous transfer formats, including both the
Motorola 6905/11 SPI and Intel 8051 SSR protocols. The inter-
face allows read/write access to all twelve registers that configure
the AD9854 and can be configured as a single pin I/O (SDIO)
or two unidirectional pins for in/out (SDIO/SDO). Data transfers
are supported in most significant bit (MSB) first format or least
significant bit (LSB) first format at up to 10 MHz.
When configured for serial I/O operation, most pins from the
AD9854 parallel port are inactive; some are used for the serial
I/O. Table VI describes pin requirements for serial I/O.
Table VI. Serial I/O Pin Requirements
Pin
Number
Pin
Name
Serial I/O Description
1, 2, 3, 4,
5, 6, 7, 8
14, 15, 16
D[7:0]
The parallel data pins are not active, tie
to VDD or GND.
The parallel address Pins A5, A4, A3
are not active, tie to VDD or GND.
IO RESET
SDO
SDIO
Update Clock. Same functionality for
Serial Mode as Parallel Mode.
SCLK
CSB—Chip Select
A[5:3]
17
18
19
20
A2
A1
A0
I/O UD
21
22
WRB
RDB
GENERAL OPERATION OF THE SERIAL INTERFACE
There are two phases to a communication cycle with the AD9854.
Phase 1 is the instruction cycle, which is the writing of an
instruction byte into the AD9854, coincident with the first eight
SCLK rising edges. The instruction byte provides the AD9854
serial port controller with information regarding the data transfer
cycle, which is Phase 2 of the communication cycle. The Phase
1 instruction byte defines whether the upcoming data transfer is
read or write, and the register address in which to transfer data
to/from.
The first eight SCLK rising edges of each communication cycle
are used to write the instruction byte into the AD9854. The
remaining SCLK edges are for Phase 2 of the communication
cycle. Phase 2 is the actual data transfer between the AD9854
and the system controller. The number of data bytes transferred
in Phase 2 of the communication cycle is a function of the regis-
ter address. The AD9854 internal serial I/O controller expects
every byte of the register being accessed to be transferred. Table
VII describes how many bytes must be transferred.
Table VII. Register Address vs. Data Bytes Transferred
Serial
Register
Address
Number
of Bytes
Transferred
Register Name
0
1
2
3
4
5
6
7
8
9
A
B
Phase Offset Tuning Word Register #1
Phase Offset Tuning Word Register #2
Frequency Tuning Word #1
Frequency Tuning Word #2
Delta Frequency Register
Update Clock Rate Register
Ramp Rate Clock Register
Control Register
I Path Digital Multiplier Register
Q Path Digital Multiplier Register
Shaped On/Off Keying Ramp Rate Register
Q DAC Register
2 Bytes
2 Bytes
6 Bytes
6 Bytes
6 Bytes
4 Bytes
3 Bytes
4 bytes
2 Bytes
2 Bytes
2 Bytes
2 Bytes
At the completion of any communication cycle, the AD9854
serial port controller expects the next eight rising SCLK edges
to be the instruction byte of the next communication cycle. In
addition, an active high input on the IO RESET pin immediately
terminates the current communication cycle. After IO RESET
returns low, the AD9854 serial port controller requires the next
eight rising SCLK edges to be the instruction byte of the next
communication cycle.
All data input to the AD9854 is registered on the rising edge of
SCLK. All data is driven out of the AD9854 on the falling edge
of SCLK.
Figures 51 and 52 are useful in understanding the general opera-
tion of the AD9854 Serial Port.
INSTRUCTION
CYCLE
DATA TRANSFER
INSTRUCTION
BYTE
DATA BYTE 1
DATA BYTE 2
DATA BYTE 3
SDIO
CS
Figure 51. Using SDIO as a Read/
Write
Transfer
INSTRUCTION
CYCLE
DATA TRANSFER
DATA BYTE 2
INSTRUCTION
BYTE
SDIO
CS
DATA TRANSFER
DATA BYTE 1
DATA BYTE 3
SDO
Figure 52. Using SDIO as an Input, SDO as an Output
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9854ASQZ | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 300MHz 2-DAC 12-Bit Parallel/Serial 80-Pin LQFP 制造商:Analog Devices 功能描述:Communication IC |
| AD9854AST | 制造商:Analog Devices 功能描述:Direct Digital Synthesizer 300MHz 2-DAC 12-Bit Parallel/Serial 80-Pin LQFP Tray 制造商:Rochester Electronics LLC 功能描述:200 MHZ QUADRATURE DDS SYNTHESIZER - Tape and Reel 制造商:Analog Devices 功能描述:IC SEMICONDUCTOR ((NS)) |
| AD9854ASTZ | 功能描述:IC DDS QUADRATURE CMOS 80-LQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 直接數(shù)字合成 (DDS) 系列:- 產(chǎn)品變化通告:Product Discontinuance 27/Oct/2011 標(biāo)準(zhǔn)包裝:2,500 系列:- 分辨率（位）:10 b 主 fclk:25MHz 調(diào)節(jié)字寬（位）:32 b 電源電壓:2.97 V ~ 5.5 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應(yīng)商設(shè)備封裝:16-TSSOP 包裝:帶卷 (TR) |
| AD9854ASVZ | 制造商:Analog Devices 功能描述:CMOS 300 MSPS QUADRATURE COMPLETE DDS 制造商:Analog Devices 功能描述:CMOS 300 MSPS QUADRATURE COMPLETE DDS - Trays 制造商:Analog Devices 功能描述:SYNTHESIZER 制造商:Analog Devices 功能描述:Complete DDS Quadrature 300MSPS TQFP80 |
| AD9854PCB | 制造商:AD 制造商全稱:Analog Devices 功能描述:CMOS 300 MSPS Quadrature Complete DDS |
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