參數(shù)資料
型號(hào)： AD9777BSV
廠商： ANALOG DEVICES INC
元件分類： DAC
英文描述： 16-Bit, 160 MSPS 2X/4X/8X Interpolating Dual TxDAC+ D/A Converter
中文描述： PARALLEL, WORD INPUT LOADING, 0.011 us SETTLING TIME, DAC WITH PROGRAMMABLE PLL, PQFP80
封裝： MO-026ADD-HD, TQFP-80
文件頁(yè)數(shù)： 20/48頁(yè)
文件大小： 6021K
代理商： AD9777BSV
REV. 0
–20–
AD9777
OFFSET REGISTER 1 ADJUSTED
DAC1, DAC2 – Offset Register Codes
–1024
–768
L
–80
0
1024
–512
–256
0
256
512
768
–70
–60
–50
–40
–30
–20
–10
OFFSET REGISTER 2
ADJUSTED, WITH OFFSET
REGISTER 1 SET
TO OPTIMIZED VALUE
Figure 9. Offset Adjust Control, Effect on LO Suppression
1R/2R MODE
In the 2R mode, the reference current for each channel is set
independently by the FSADJ resistor on that channel. The
AD9777 can be programmed to derive its reference current from a
single resistor on Pin 60 by placing the part in the 1R mode. The
transfer functions in Equation 1 are valid for the 2R mode. In the
1R mode, the current developed in the single FSADJ resistor is
split equally between the two channels. The result is that in the
1R mode, a scale factor of one-half must be applied to the formulas
in Equation 1. The full-scale DAC current in the 1R mode can still
be set to as high as 20 mA by using the internal 1.2 V reference and
a 950
resistor, instead of the 1.9 k
resistor typically used
in the 2R mode.
CLOCK INPUT CONFIGURATIONS
The clock inputs to the AD9777 can be driven differentially or
single-ended. The internal clock circuitry has supply and ground
(CLKVDD, CLKGND) separate from the other supplies on the
chip to minimize jitter from internal noise sources.
Figure 10 shows the AD9777 driven from a single-ended clock
source. The CLK+/CLK– Pins form a differential input (CLKIN),
so that the statically terminated input must be dc-biased to the
midswing voltage level of the clock driven input.
R
SERIES
V
THRESHOLD
AD9777
CLK+
CLKVDD
CLK–
CLKGND
0.1 F
Figure 10. Single-Ended Clock Driving Clock
Inputs
A configuration for differentially driving the clock inputs is
given in Figure 11. DC-blocking capacitors can be used to
couple a clock driver output whose voltage swings exceed
CLKVDD or CLKGND. If the driver voltage swings are within
the supply range of the AD9777, the dc-blocking capacitors
and bias resistors are not necessary.
AD9777
CLK+
CLKVDD
CLK–
CLKGND
0.1 F
1k
ECL/PECL
1k
1k
1k
0.1 F
0.1 F
Figure 11. Differential Clock Driving Clock Inputs
A transformer, such as the T1-1T from Mini-Circuits, can also be
used to convert a single-ended clock to differential. This method is
used on the AD9777 evaluation board so that an external sine
wave with no dc offset can be used as a differential clock.
PECL/ECL drivers require varying termination networks, the
details of which are left out of Figures 10 and 11 but can be found
in application notes such as AND8020/D from On Semiconductor.
These networks depend on the assumed transmission line imped-
ance and power supply voltage of the clock driver. Optimum
performance of the AD9777 is achieved when the driver is placed
very close to the AD9777 clock inputs, thereby negating any
transmission line effects such as reflections due to mismatch.
The quality of the clock and data input signals is important in
achieving optimum performance. The external clock driver cir-
cuitry should provide the AD9777 with a low jitter clock input
that meets the min/max logic levels while providing fast edges.
Although fast clock edges help minimize any jitter that will manifest
itself as phase noise on a reconstructed waveform, the high gain
bandwidth product of the AD9777’s differential comparator can
tolerate sine wave inputs as low as 0.5 V p-p, with minimal
degradation of the output noise floor.
PROGRAMMABLE PLL
CLKIN can function either as an input data rate clock (PLL
enabled) or as a DAC data rate clock (PLL disabled) according
to the state of Address 02h, Bit 7 in the SPI port register. The
internal operation of the AD9777 clock circuitry in these two
modes is illustrated in Figures 12 and 13.
The PLL clock multiplier and distribution circuitry produce the
necessary internal synchronized 1
×
, 2
×
, 4
×
, and 8
×
clocks for the
rising edge triggered latches, interpolation filters, modulators, and
DACs. This circuitry consists of a phase detector, charge pump,
voltage controlled oscillator (VCO), prescaler, clock distribution,
and SPI port control. The charge pump and VCO are powered
from PLLVDD while the differential clock input buffer, phase
detector, prescaler, and clock distribution are powered from
CLKVDD. PLL lock status is indicated by the logic signal at the
PLL_LOCK Pin, as well as by the status of Bit 1, Register 00h.
To ensure optimum phase noise performance from the PLL clock
multiplier, and distribution, PLLVDD and CLKVDD should
originate from the same clean analog supply. The speed of the
VCO with the PLL enabled also has an effect on phase noise.
Optimal phase noise with respect to VCO speed is achieved by
running the VCO in the range of 450 MHz to 550 MHz. The
VCO speed is a function of the input data rate, the interpolation
rate, and the VCO prescaler, according to the following function:
VCO Speed MHz
Input Data Rate MHz
InterpolationRate
escaler
(
)
(
)
=
×
×
Pr
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相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9777BSVRL 制造商:Analog Devices 功能描述:DAC 2-CH R-2R 16-bit 80-Pin TQFP EP T/R
AD9777BSVZ 功能描述:IC DAC 16BIT DUAL 160MSPS 80TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC+® 標(biāo)準(zhǔn)包裝:1 系列:- 設(shè)置時(shí)間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉(zhuǎn)換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應(yīng)商設(shè)備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND
AD9777BSVZ 制造商:Analog Devices 功能描述:IC 16-BIT DAC ((NW)) 制造商:Analog Devices 功能描述:IC, DAC, 16BIT, 400MSPS, TQFP-80
AD9777BSVZ 制造商:Analog Devices 功能描述:IC DAC 16BIT 400MSPS 80TQFP
AD9777BSVZRL 功能描述:IC DAC 16BIT DUAL 160MSPS 80TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC+® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1,000 系列:- 設(shè)置時(shí)間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:*
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