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參數資料
| 型號： | AD9777BSV |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 16-Bit, 160 MSPS 2X/4X/8X Interpolating Dual TxDAC+ D/A Converter |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 0.011 us SETTLING TIME, DAC WITH PROGRAMMABLE PLL, PQFP80 |
| 封裝： | MO-026ADD-HD, TQFP-80 |
| 文件頁數： | 15/48頁 |
| 文件大小： | 6021K |
| 代理商： | AD9777BSV |
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REV. 0
AD9777
–15–
Address 03h
Bits 1, 0
Setting this divide ratio to a higher number allows
the VCO in the PLL to run at a high rate (for best
performance) while the DAC input and output
clocks run substantially slower. The divider ratio is
set according to the following table:
00
1
01
2
10
4
11
8
Address 04h
Bit 7
Logic “0” (default) disables the internal PLL.
Logic “1” enables the PLL.
Bit 6
Logic “0” (default) sets the charge pump control to
automatic. In this mode, the charge pump bias
current is controlled by the divider ratio defined in
Address 03h, Bits 1 and 0. Logic “1” allows the
user to manually define the charge pump bias cur-
rent using Address 04h, Bits 2, 1, and 0. Adjusting
the charge pump bias current allows the user to
optimize the noise/settling performance of the PLL.
Bits 2, 1, 0 With the charge pump control set to manual, these
bits define the charge pump bias current according
to the following table:
000
50
μ
A
001
100
μ
A
010
200
μ
A
011
400
μ
A
100
800
μ
A
Address 05h, 09h
Bits 7–0
These bits represent an 8-bit binary number (Bit 7
MSB) that defines the fine gain adjustment of the I
(05h) and Q (09h) DAC according to the equation
given below.
Address 06h, 0Ah
Bits 3–0
These bits represent a 4-bit binary number (Bit 3
MSB) that defines the coarse gain adjustment of the
I (06h) and Q (0Ah) DACs according to the equa-
tion below.
Address 07h, 0Bh
Bits 7–0
Address 08h, 0Ch
Bits 1, 0
The 10 bits from these two address pairs (07h, 08h
and 0Bh, 0Ch) represent a 10-bit binary number that
defines the offset adjustment of the I and Q DACs
according to the equation below
(07h, 0Bh–Bit 7 MSB/08h, 0Ch–Bit 0 LSB).
Address 08h, 0Ch
Bit 7
This bit determines the direction of the offset of the
I (08h) and Q (0Ch) DACs. A Logic “0” will apply
a positive offset current to I
OUTA
, while a Logic “1”
will apply a positive offset current to I
OUTB
. The
magnitude of the offset current is defined by the
bits in Addresses 07h, 0Bh, 08h, 0Ch according to
the formulas given below.
I
I
8
COARSE
I
FINE
256
DATA
2
I
I
8
COARSE
I
FINE
256
OUTA
REF
REF
OUTB
REF
REF
=
×
+
×
=
×
+
×
6
1
16
3
32
1024
24
6
1
16
3
32
16
–
–
=
×
1024
24
2
1
2
4
1024
16
16
–
–
DATA
I
I
OFFSET
OFFSET
REF
(1)
Equation 1 shows
I
OUTA
and
I
OUTB
as a function of fine gain, coarse gain, and offset adjustment when using the 2R mode. In the 1R
mode, the current
I
REF
is created by a single FSADJ resistor (Pin 60). This current is divided equally into each channel so that a
scaling factor of one-half must be added to these equations for full-scale currents for both DACs and the offset.
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