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參數(shù)資料
| 型號： | AD9777BSV |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | DAC |
| 英文描述： | 16-Bit, 160 MSPS 2X/4X/8X Interpolating Dual TxDAC+ D/A Converter |
| 中文描述： | PARALLEL, WORD INPUT LOADING, 0.011 us SETTLING TIME, DAC WITH PROGRAMMABLE PLL, PQFP80 |
| 封裝： | MO-026ADD-HD, TQFP-80 |
| 文件頁數(shù)： | 19/48頁 |
| 文件大?。?/td> | 6021K |
| 代理商： | AD9777BSV |
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REV. 0
AD9777
–19–
The offset control defines a small current that can be added
to I
OUTA
or I
OUTB
(not both) on the IDAC and QDAC. The
selection of which I
OUT
this offset current is directed toward is
programmable via Register 08h, Bit 7 (IDAC) and Register 0Ch,
Bit 7 (QDAC). Figure 9 shows the scale of the offset current
that can be added to one of the complementary outputs on the
IDAC and QDAC. Offset control can be used for suppression of
LO leakage resulting from modulation of dc signal components.
If the AD9777 is dc-coupled to an external modulator, this
feature can be used to cancel the output offset on the AD9777
as well as the input offset on the modulator. Figure 9 shows a
typical example of the effect that the offset control has on LO
suppression.
OFFSET
DAC
QDAC
IDAC
OFFSET
DAC
REFIO
0.1 F
FSADJ1
FSADJ2
RSET1
RSET2
I
OUTA1
I
OUTB1
OFFSET
CONTROL
REGISTERS
I
OUTA2
I
OUTB2
GAIN
CONTROL
REGISTERS
COARSE
GAIN
DAC
COARSE
GAIN
DAC
FINE
GAIN
DAC
FINE
GAIN
DAC
1.2VREF
GAIN
CONTROL
REGISTERS
OFFSET
CONTROL
REGISTERS
Figure 6. DAC Outputs, Reference Current Scaling, and
Gain/Offset Adjust
COARSE GAIN REGISTER CODE – Assuming
RSET1, 2 = 1.9k
0
5
C
0
25
10
15
20
5
10
15
20
2R MODE
1R MODE
Figure 7a. Coarse Gain Effect on I
FULLSCALE
FINE GAIN REGISTER CODE – Assuming
RSET1, 2 = 1.9k
0
5
F
–3.0
10
15
20
2R MODE
1R MODE
–2.5
–2.0
–1.5
–1.0
–0.5
0
Figure 7b. Fine Gain Effect on I
FULLSCALE
In Figure 9, the negative scale represents an offset added to
I
OUTB
, while the
positive scale represents an offset added to
I
OUTA
of the respective DAC. Offset Register 1 corresponds
to IDAC, while Offset Register 2 corresponds to QDAC. Figure 9
represents the AD9777 synthesizing a complex signal that is
then dc-coupled to an AD8345 quadrature modulator with an
LO of 800 MHz. The dc-coupling allows the input offset of the
AD8345 to be calibrated out as well. The LO suppression at the
AD8345 output was optimized first by adjusting Offset Register 1,
in the AD9777. When an optimal point was found (roughly
Code 54), this code was held in Offset Register 1, and
Offset Register 2 was adjusted. The resulting LO suppression is
70 dBFS. These are typical numbers, and the specific code for
optimization will vary from part to part.
COARSE GAIN REGISTER CODE – Assuming
RSET1, 2 = 1.9k
0
200
O
0
5
400
600
800
1
2
3
4
2R MODE
1R MODE
1000
Figure 8. DAC Output Offset Current
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|---|---|
| AD9777BSVRL | 制造商:Analog Devices 功能描述:DAC 2-CH R-2R 16-bit 80-Pin TQFP EP T/R |
| AD9777BSVZ | 功能描述:IC DAC 16BIT DUAL 160MSPS 80TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉換器 系列:TxDAC+® 標準包裝:1 系列:- 設置時間:4.5µs 位數(shù):12 數(shù)據(jù)接口:串行，SPI? 轉換器數(shù)目:1 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 125°C 安裝類型:表面貼裝 封裝/外殼:8-SOIC（0.154"，3.90mm 寬） 供應商設備封裝:8-SOICN 包裝:剪切帶 (CT) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:* 其它名稱:MCP4921T-E/SNCTMCP4921T-E/SNRCTMCP4921T-E/SNRCT-ND |
| AD9777BSVZ | 制造商:Analog Devices 功能描述:IC 16-BIT DAC ((NW)) 制造商:Analog Devices 功能描述:IC, DAC, 16BIT, 400MSPS, TQFP-80 |
| AD9777BSVZ | 制造商:Analog Devices 功能描述:IC DAC 16BIT 400MSPS 80TQFP |
| AD9777BSVZRL | 功能描述:IC DAC 16BIT DUAL 160MSPS 80TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉換器 系列:TxDAC+® 產(chǎn)品培訓模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標準包裝:1,000 系列:- 設置時間:1µs 位數(shù):8 數(shù)據(jù)接口:串行 轉換器數(shù)目:8 電壓電源:雙 ± 功率耗散（最大）:941mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC W 包裝:帶卷 (TR) 輸出數(shù)目和類型:8 電壓，單極 采樣率（每秒）:* |
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