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參數(shù)資料
| 型號： | AD9775EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 14-Bit, 160 MSPS 2X/4X/8X Interpolating Dual TxDAC+ D/A Converter |
| 中文描述： | 14位，160 MSPS的2X/4X/8X TxDAC系列插雙D / A轉(zhuǎn)換 |
| 文件頁數(shù)： | 7/48頁 |
| 文件大?。?/td> | 6054K |
| 代理商： | AD9775EB |
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REV. 0
AD9775
–7–
PIN FUNCTION DESCRIPTIONS
Pin Number
Mnemonic
Description
1, 3
2
4, 7
5
6
8
CLKVDD
LPF
CLKGND
CLK+
CLK–
DATACLK/PLL_LOCK
Clock Supply Voltage
PLL Loop Filter
Clock Supply Common
Differential Clock Input
Differential Clock Input
With the PLL enabled, this pin indicates the state of the PLL. A read of a
Logic “1” indicates the PLL is in the locked state. Logic “0” indicates the
PLL has not achieved lock. This pin may also be programmed to act as
either an input or output (Address 02h, Bit 3) DATACLK signal running at
the input data rate.
Digital Common
Digital Supply Voltage
P1B13 (MSB) to P1B0 (LSB) Port “1” Data Inputs
NC
No Connect
IQSEL/P2B13 (MSB)
In “1” port mode, IQSEL = 1 followed by a rising edge of the differential
input clock will latch the data into the I channel input register. IQSEL = 0
will latch the data into the Q channel input register. In “2” port mode, this
pin becomes the port “2” MSB.
ONEPORTCLK/P2B12
With the PLL disabled and the AD9775 in “1” port mode, this pin becomes
a clock output that runs at twice the input data rate of the I and Q channels.
This allows the AD9775 to accept and demux interleaved I and Q data to
the I and Q input registers.
P2B11 to P2B0 (LSB)
Port “2” Data Inputs
SPI_SDO
In the case where SDIO is an input, SDO acts as an output. When SDIO
becomes an output, SDO enters a High-Z state.
SPI_SDIO
Bidirectional Data Pin. Data direction is controlled by Bit 7 of Register
Address 00h. The default setting for this bit is “0,” which sets SDIO as an input.
SPI_CLK
Data input to the SPI port is registered on the rising edge of SPI_CLK.
Data output on the SPI port is registered on the falling edge.
SPI_CSB
Chip Select/SPI Data Synchronization. On momentary logic high, resets
SPI port logic and initializes instruction cycle.
RESET
Logic “1” resets all of the SPI port registers, including Address 00h, to their
default values. A software reset can also be done by writing a Logic “1” to
SPI Register 00h, Bit 5. However, the software reset has no effect on the bits
in Address 00h.
REFIO
Reference Output, 1.2 V Nominal
FSADJ2
Full-Scale Current Adjust, Q Channel
FSADJ1
Full-Scale Current Adjust, I Channel
AVDD
Analog Supply Voltage
62, 64, 66, 67, 70, 71, AGND
Analog Common
74, 75, 77, 79
68, 69
I
OUTA2
, I
OUTB2
Differential DAC Current Outputs, Q Channel
72, 73
I
OUTA1
, I
OUTB1
Differential DAC Current Outputs, I Channel
9, 17, 25, 35, 44, 52
10, 18, 26, 36, 43, 51
11–16, 19–24, 27, 28
29, 30, 49, 50
31
DGND
DVDD
32
33, 34, 37–42, 45–48
53
54
55
56
57
58
59
60
61, 63, 65, 76, 78, 80
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9775-EB | 制造商:Analog Devices 功能描述:EVAL BOARD - Bulk |
| AD9775-EBZ | 功能描述:BOARD EVALUATION FOR AD9775 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:TxDAC+® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
| AD9776 | 制造商:AD 制造商全稱:Analog Devices 功能描述:400 MHz to 6 GHz Broadband Quadrature Modulator |
| AD9776A | 制造商:AD 制造商全稱:Analog Devices 功能描述:Dual, 12-/14-/16-Bit,1 GSPS Digital-to-Analog Converters |
| AD9776ABSVZ | 功能描述:IC DAC 12BIT 1.0GSPS 100TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 設(shè)置時間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF) |
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