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參數(shù)資料
| 型號： | AD9775EB |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 14-Bit, 160 MSPS 2X/4X/8X Interpolating Dual TxDAC+ D/A Converter |
| 中文描述： | 14位，160 MSPS的2X/4X/8X TxDAC系列插雙D / A轉(zhuǎn)換 |
| 文件頁數(shù)： | 23/48頁 |
| 文件大小： | 6054K |
| 代理商： | AD9775EB |
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REV. 0
AD9775
–23–
CLKIN
DATACLK
DATA AT PORTS
1 AND 2
t
OD
t
H
t
S
t
S
= 0.0ns
t
= 2.5ns
(TYP SPECS)
Figure 18. Timing Requirements in Two Port
Input Mode, with PLL Enabled
DATACLK DRIVER STRENGTH
(Control Register 02h, Bit 5)
The DATACLK output driver strength is capable of driving
>10 mA into a 330
load while providing a rise time of 3 ns.
Figure 19 shows DATACLK driving a 330
resistive load at a
frequency of 50 MHz. By enabling the drive strength option
(Control Register 02h, Bit 5), the amplitude of DATACLK
under these conditions will be increased by approximately 200 mV.
TIME – ns
0
10
F
–0.5
20
30
40
0
0.5
1.0
1.5
2.0
2.5
3.0
50
DELTA APPROX. 2.8ns
Figure 19. DATACLK Driver Capability into 330
at 50 MHz
PLL ENABLED, ONE PORT MODE
(Control Register 02h, Bits 6–1 and 04h, Bits 7–1)
In one port mode, the I and Q channels receive their data from an
interleaved stream at digital input Port 1. The function of Pin 32
is defined as an output (ONEPORTCLK) that generates a clock at
the interleaved data rate which is 2
×
the internal input data
rate of the I and Q channels. The frequency of CLKIN is equal
to the internal input data rate of the I and Q channels. The
selection of the data for the I or the Q channel is determined by the
state of the logic level at Pin 31 (IQSEL when the AD9775 is in
one port mode) on the rising edge of ONEPORTCLK. IQSEL
= 1 under these conditions will latch the data into the I channel
on the clock rising edge, while IQSEL = 0 will latch the data into
the Q channel. It is possible to invert the I and Q selection by set-
ting control Register 02h, Bit 1 to the invert state (Logic “1”).
Figure 20 illustrates the timing requirements for the data inputs as
well as the IQSEL input. Note that the 1
×
interpolation rate is
not available in the one port mode.
The DAC output sample rate in one port mode is equal to CLKIN
multiplied by the interpolation rate. If zero stuffing is used, another
factor of two must be included to calculate the DAC sample rate.
ONEPORTCLK INVERSION
(Control Register 02h, Bit 2)
By programming this bit, the ONEPORTCLK signal shown in
Figure 20 can be inverted. With inversion enabled, t
OD
refers to
the delay between the rising edge of the external clock and the
falling edge of ONEPORTCLK. The setup and hold times, t
S
and
t
H
,
will be with respect to the falling edge of ONEPORTCLK.
There will be no other effect on timing.
ONEPORTCLK DRIVER STRENGTH
The drive capability of ONEPORTCLK is identical to that of
DATACLK in the two port mode. Refer to Figure 19 for perfor-
mance under load conditions.
t
OD
t
H
t
S
CLKIN
I AND Q INTERLEAVED
INPUT DATA AT PORT 1
ONEPORTCLK
IQSEL
t
IQH
t
IQS
t
OD
= 4.7ns
t
S
= 3.0ns
t
H
= –0.5ns
t
IQS
= 3.5ns
t
IQH
= –1.5ns
Figure 20. Timing Requirements in One Port
Input Mode with the PLL Enabled
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9775-EB | 制造商:Analog Devices 功能描述:EVAL BOARD - Bulk |
| AD9775-EBZ | 功能描述:BOARD EVALUATION FOR AD9775 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估板 - 數(shù)模轉(zhuǎn)換器 (DAC) 系列:TxDAC+® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:1 系列:- DAC 的數(shù)量:4 位數(shù):12 采樣率（每秒）:- 數(shù)據(jù)接口:串行，SPI? 設(shè)置時間:3µs DAC 型:電流/電壓 工作溫度:-40°C ~ 85°C 已供物品:板 已用 IC / 零件:MAX5581 |
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| AD9776ABSVZ | 功能描述:IC DAC 12BIT 1.0GSPS 100TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 設(shè)置時間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF) |
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