參數(shù)資料
型號(hào): AD9775EB
廠商: Analog Devices, Inc.
英文描述: 14-Bit, 160 MSPS 2X/4X/8X Interpolating Dual TxDAC+ D/A Converter
中文描述: 14位,160 MSPS的2X/4X/8X TxDAC系列插雙D / A轉(zhuǎn)換
文件頁(yè)數(shù): 13/48頁(yè)
文件大?。?/td> 6054K
代理商: AD9775EB
REV. 0
AD9775
–13–
MODE CONTROL (VIA SPI PORT)
Table I. Mode Control via SPI Port
(Default Values Are Highlighted)
Address
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
00h
SDIO
Bidirectional
0 = Input
1 = I/O
LSB, MSB First
0 = MSB
1 = LSB
Software Reset on
Logic “1”
Sleep Mode
Logic “1” shuts down
the DAC output
currents.
Power-Down Mode
Logic “1” shuts down
all digital and analog
functions.
1R/2R Mode
DAC output current set
by one or two external
resistors.
0 = 2R
, 1 = 1R
PLL_LOCK
Indicator
01h
Filter
Interpolation
Rate
(1
×
, 2
×
, 4
×
, 8
×
)
Filter
Interpolation
Rate
(1
×
, 2
×
, 4
×
, 8
×
)
Modulation
Mode
(
None
, f
S
/2,
f
S
/4, f
S
/8)
Modulation Mode
(
None
, f
S
/2, f
S
/4, f
S
/8)
0 = No Zero Stuffing
on Interpolation
Filters
, Logic “1”
enables zero stuffing.
1 = Real Mix Mode
0 = Complex
Mix Mode
0 = e
–j
1 = e
+j
DATACLK/
PLL_LOCK
Select
0 = PLLLOCK
1 = DATACLK
02h
0 = Signed Input
Data
1 = Unsigned
0 = Two Port Mode
1 = One Port Mode
DATACLK Driver
Strength
DATACLK Invert
0 = No Invert
1 = Invert
ONEPORTCLK Invert
0 = No Invert
1 = Invert
IQSEL Invert
0 = No Invert
1 = Invert
Q First
0 = I First
1 = Q First
03h
PLL Divide
(Prescaler) Ratio
PLL Divide
(Prescaler) Ratio
04h
0 = PLL OFF
1 = PLL ON
0 = Automatic
Charge Pump Control
1 = Programmable
PLL Charge Pump
Control
PLL Charge Pump
Control
PLL Charge Pump
Control
05h
IDAC Fine Gain
Adjustment
IDAC Fine Gain
Adjustment
IDAC Fine Gain
Adjustment
IDAC Fine Gain
Adjustment
IDAC Fine Gain
Adjustment
IDAC Fine Gain
Adjustment
IDAC Fine Gain
Adjustment
IDAC Fine Gain
Adjustment
06h
IDAC Coarse Gain
Adjustment
IDAC Coarse Gain
Adjustment
IDAC Coarse Gain
Adjustment
IDAC Coarse Gain
Adjustment
07h
IDAC Offset
Adjustment Bit 9
IDAC Offset
Adjustment Bit 8
IDAC Offset
Adjustment Bit 7
IDAC Offset
Adjustment Bit 6
IDAC Offset
Adjustment Bit 5
IDAC Offset
Adjustment Bit 4
IDAC Offset
Adjustment Bit 3
IDAC Offset
Adjustment Bit 2
08h
IDAC I
OFFSET
Direction
0 = I
OFFSET
on I
OUTA
1 = I
OFFSET
on
I
OUTB
IDAC Offset
Adjustment Bit 1
IDAC Offset
Adjustment Bit 0
09h
QDAC Fine Gain
Adjustment
QDAC Fine Gain
Adjustment
QDAC Fine Gain
Adjustment
QDAC Fine Gain
Adjustment
QDAC Fine Gain
Adjustment
QDAC Fine Gain
Adjustment
QDAC Fine Gain
Adjustment
QDAC Fine Gain
Adjustment
0Ah
QDAC Coarse
Gain Adjustment
QDAC Coarse
Gain Adjustment
QDAC Coarse
Gain Adjustment
QDAC Coarse
Gain Adjustment
0Bh
QDAC Offset
Adjustment Bit 9
QDAC Offset
Adjustment Bit 8
QDAC Offset
Adjustment Bit 7
QDAC Offset
Adjustment Bit 6
QDAC Offset
Adjustment Bit 5
QDAC Offset
Adjustment Bit 4
QDAC Offset
Adjustment Bit 3
QDAC Offset
Adjustment Bit 2
0Ch
QDAC I
OFFSET
Direction
0 = I
OFFSET
on I
OUTA
1 = I
OFFSET
on I
OUTB
QDAC Offset
Adjustment Bit 1
QDAC Offset
Adjustment Bit 0
0Dh
Version Register
Version Register
Version Register
Version Register
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