參數(shù)資料
型號(hào)： AD9772A
廠商： Analog Devices, Inc.
英文描述： 14-Bit, 160 MSPS TxDAC+ with 2x Interpolation Filter
中文描述： 14位，160 MSPS的TxDAC系列的2倍插值濾波器
文件頁(yè)數(shù)： 24/32頁(yè)
文件大?。?/td> 596K
代理商： AD9772A
REV. A
AD9772A
–24–
A
OUT
–
dBFS
90
85
60
–
14
S
–
80
75
70
65
–
12
–
10
–
8
–
6
–
2
–
4
0
55
50
325MHz
275MHz
75MHz
125MHz
Figure 35. Dual-Tone “Windowed” SFDR vs. A
OUT
@
f
DATA
= 100 MSPS
For many applications, the data update rate to the DAC (i.e.,
f
DATA
) must be some fixed integer multiple of some system
reference clock (i.e., GSM
–
13 MHz). Furthermore, these
applications prefer to use standard IF frequencies which offer
a large selection of SAW filter choices of varying passbands
(i.e., 70 MHz). These applications may still benefit from the
AD9772A
’
s direct IF mode capabilities when used in conjunc-
tion with a digital upconverter such as the AD6622. Since the
AD6622 can digitally synthesize and tune up to four modulated
carriers, it is possible to judiciously tune these carriers in a region
which may fall within an IF filter
’
s passband upon reconstruc-
tion by the AD9772A. Figure 36 shows an example in which
four carriers were tuned around 18 MHz with a digital upcon-
verter operating at 52 MSPS such that when reconstructed by
the AD9772A in the IF MODE, these carriers fall around a
70 MHz IF.
FREQUENCY
–
MHz
–
10
–
110
66
A
–
–
30
–
50
–
70
–
90
68
70
72
74
–
80
–
60
–
40
–
20
Figure 36. Spectral Plot of Four Carriers at 60 MHz IF
with f
DATA
= 52 MSPS, PLLVDD = 0
AD9772A EVALUATION BOARD
The AD9772-EB is an evaluation board for the AD9772A TxDAC.
Careful attention to layout and circuit design, combined with
prototyping area, allows the user to easily and effectively evalu-
ate the AD9772A in different modes of operation.
Referring to Figures 37 and 38, the AD9772A
’
s performance
can be evaluated differentially or single-endedly using a trans-
former, differential amplifier, or directly coupled output. To
evaluate the output differentially using the transformer, remove
jumpers JP12 and JP13 and monitor the output at J6 (IOUT).
To evaluate the output differentially, remove the transformer
(T2) and install jumpers JP12 and JP13. The output of the
amplifier can be evaluated at J13 (AMPOUT). To evaluate the
AD9772A single-endedly and directly coupled, remove the
transformer and jumpers (JP12 and JP13) and install resistors
R16 or R17 with 0
.
The digital data to the AD9772A comes across a ribbon cable
which interfaces to a 40-pin IDC connector. Proper termination
or voltage scaling can be accomplished by installing RN2 and/or
RN3 SIP resistor networks. The 22
DIP resistor network,
RN1, must be installed and helps reduce the digital data edge
rates. A single-ended CLOCK input can be supplied via the
ribbon cable by installing JP8 or more preferably via the SMA
connector, J3 (CLOCK). If the CLOCK is supplied by J3, the
AD9772A can be configured for a differential clock interface by
installing jumpers JP1 and configuring JP2, JP3, and JP9 for the
DF position. To configure the AD9772A clock input for a single-
ended clock interface, remove JP1 and configure JP2, JP3 and
JP9 for the SE position.
The AD9772A
’
s PLL clock multiplier can be disabled by con-
figuring jumper JP5 for the L position. In this case, the user
must supply a clock input at twice (2 ) the data rate via J3
(CLOCK). The 1 clock is made available on SMA con-
nector J1 (PLLLOCK), and should be used to trigger a pattern
generator directly or via a programmable pulse generator. Note
that PLLLOCK is capable of providing a 0 V to 0.85 V output
into a 50
load. To enable the PLL clock multiplier, JP5 must
be configured for the H position. In this case, the clock may be
supplied via the ribbon cable (i.e., JP8 installed) or J3 (CLOCK).
The divide-by-N ratio can be set by configuring JP6 (DIV0) and
JP7 (DIV1).
The AD9772A can be configured for Baseband or Direct IF Mode
operation by configuring jumpers JP11 (MOD0) and JP10
(MOD1). For baseband operation, JP10 and JP11 should be
configured in the L position. For direct IF operation, JP10 and
JP11 should be configured in the H position. For direct IF
operation without
“
zero-stuffing,
”
JP11 should be configured in
the H position while JP10 should be configured in the low position.
The AD9772A
’
s voltage reference can be enabled or disabled
via JP4 (EXT REF IN). To enable the reference, configure JP in
the INT position. A voltage of approximately 1.2 V will appear
at the TP6 (REFIO) test point. To disable the internal refer-
ence, configure JP4 in the EXT position and drive TP6 with an
external voltage reference. Lastly, the AD9772A can be placed
in the SLEEP mode by driving the TP11 test point with logic
level HIGH input signal.
相關(guān)PDF資料
PDF描述
AD9772AAST 14-Bit, 160 MSPS TxDAC+ with 2x Interpolation Filter
AD9772 14-Bit,150 MSPS T×DAC+TM with 2× Interpolation Filter(單電源,過(guò)采樣,14位D/A轉(zhuǎn)換器)
AD9773 12-Bit, 160 MSPS 2】/4】/8】 Interpolating Dual TxDAC+ D/A Converter
AD9773AST 12-Bit, 160 MSPS 2】/4】/8】 Interpolating Dual TxDAC+ D/A Converter
AD9773EB 12-Bit, 160 MSPS 2】/4】/8】 Interpolating Dual TxDAC+ D/A Converter
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
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AD9772AASTRL 制造商:Analog Devices 功能描述:DAC 1-CH Segment 14-bit 48-Pin LQFP T/R
AD9772AASTZ 功能描述:IC DAC 14BIT 160MSPS 48-LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC+® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 設(shè)置時(shí)間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類(lèi)型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類(lèi)型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁(yè)面:1398 (CN2011-ZH PDF)
AD9772AASTZRL 功能描述:IC DAC 14BIT 160MSPS 48LQFP RoHS:是 類(lèi)別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC+® 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時(shí)間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類(lèi)型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類(lèi)型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k
AD9772A-EB 制造商:Analog Devices 功能描述:14 BIT DAC W/2X INTERPOLATION 制造商:Analog Devices 功能描述:DEV TOOLS, EVAL BD FOR AD9772A - Bulk
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