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參數(shù)資料
| 型號(hào)： | AD9772A |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 14-Bit, 160 MSPS TxDAC+ with 2x Interpolation Filter |
| 中文描述： | 14位，160 MSPS的TxDAC系列的2倍插值濾波器 |
| 文件頁數(shù)： | 18/32頁 |
| 文件大?。?/td> | 596K |
| 代理商： | AD9772A |
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REV. A
AD9772A
–18–
Operating the AD9772A with reduced voltage output swings at
I
OUTA
and I
OUTB
in a differential or single-ended output configu-
ration reduces the signal dependency of its output impedance,
thus enhancing distortion performance. Although the voltage
compliance range of I
OUTA
and I
OUTB
extends from
–
1.0 V to
+1.25 V, optimum distortion performance is achieved when the
maximum full-scale signal at I
OUTA
and I
OUTB
does not exceed
approximately 0.5 V. A properly selected transformer with a
grounded center-tap will allow the AD9772A to provide the
required power and voltage levels to different loads while main-
taining reduced voltage swings at I
OUTA
and I
OUTB
. DC-coupled
applications requiring a differential or single-ended output con-
figuration should size R
LOAD
accordingly. Refer to Applying the
AD9772A section for examples of various output configurations.
The most significant improvement in the AD9772A
’
s distortion
and noise performance is realized using a differential output
configuration. The common-mode error sources of both I
OUTA
and
I
OUTB
can be substantially reduced by the common-mode rejection
of a transformer or differential amplifier. These common-
mode error sources include even-order distortion products
and noise. The enhancement in distortion performance becomes
more significant as the reconstructed waveform
’
s frequency
content increases and/or its amplitude decreases. The distor-
tion and noise performance of the AD9772A is also dependent
on the full-scale current setting, I
OUTFS
. Although I
OUTFS
can be
set between 2 mA and 20 mA, selecting an I
OUTFS
of 20 mA will
provide the best distortion and noise performance.
In summary, the AD9772A achieves the optimum distortion
and noise performance under the following conditions:
1. Positive voltage swing at I
OUTA
and I
OUTB
limited to 0.5 V.
2. Differential Operation.
3. I
OUTFS
set to 20 mA.
4. PLL Clock Multiplier Disabled
Note the majority of the AC Characterization Curves for the
AD9772A are performed under the above-mentioned operating
conditions.
DIGITAL INPUTS/OUTPUTS
The AD9772A consists of several digital input pins used for
data, clock, and control purposes. It also contains a single digi-
tal output pin, PLLLOCK, used to monitor the status of the
internal PLL clock multiplier or provide a 1
clock output. The
14-bit parallel data inputs follow standard positive binary coding
where DB13 is the most significant bit (MSB), and DB0 is the
least significant bit (LSB). I
OUTA
produces a full-scale output
current when all data bits are at Logic 1. I
OUTB
produces a
complementary output with the full-scale current split between
the two outputs as a function of the input code.
The digital interface is implemented using an edge-triggered
master slave latch and is designed to support an input data rate
as high as 160 MSPS. The clock can be operated at any duty
cycle that meets the specified latch pulsewidth as shown in
Figures 1a and 1b. The setup and hold times can also be varied
within the clock cycle as long as the specified minimum times
are met. The digital inputs (excluding CLK+ and CLK
–
) are
CMOS-compatible with its logic thresholds, V
THRESHOLD,
set to
approximately half the digital positive supply (i.e., DVDD or
CLKVDD) or
V
THRESHOLD
= DVDD
/2 (
±
20%)
The internal digital circuitry of the AD9772A is capable of operat-
ing over a digital supply range of 2.8 V to 3.2 V. As a result, the
digital inputs can also accommodate TTL levels when DVDD is
set to accommodate the maximum high level voltage of the TTL
drivers V
OH(MAX)
. Although a DVDD of 3.3 V will typically ensure
proper compatibility with most TTL logic families, a series
200
resistors are recommended between the TTL logic driver
and digital inputs to limit the peak current through the ESD pro-
tection diodes if V
OH(MAX)
exceeds DVDD by more than 300 mV.
Figure 19 shows the equivalent digital input circuit for the data
and control inputs.
DIGITAL
INPUT
DVDD
Figure 19. Equivalent Digital Input
The AD9772A features a flexible differential clock input oper-
ating from separate supplies (i.e., CLKVDD, CLKCOM) to
achieve optimum jitter performance. The two clock inputs,
CLK+ and CLK
–
, can be driven from a single-ended or differen-
tial clock source. For single-ended operation, CLK+ should be
driven by a single-ended logic source while CLK
–
should be set
to the logic source
’
s threshold voltage via a resistor divider/capaci-
tor network referenced to CLKVDD as shown in Figure 20. For
differential operation, both CLK+ and CLK
–
should be biased to
CLKVDD/2 via a resistor divider network as shown in Figure 21.
An RF transformer as shown in Figure 3 can also be used to
convert a single-ended clock input to a differential clock input.
R
SERIES
V
THRESHOLD
AD9772A
CLK+
CLKVDD
CLK
–
CLKCOM
0.1 F
1k
1k
Figure 20. Single-Ended Clock Interface
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PDF描述 |
|---|---|
| AD9772AAST | 14-Bit, 160 MSPS TxDAC+ with 2x Interpolation Filter |
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9772AAST | 制造商:Analog Devices 功能描述:DAC 1-CH Segment 14-bit 48-Pin LQFP 制造商:Rochester Electronics LLC 功能描述:14BIT 160 MSPS TXDAC+ W/2X INTERPOLATION - Tape and Reel 制造商:Analog Devices 功能描述:Digital-Analog Converter IC Number of Bi |
| AD9772AASTRL | 制造商:Analog Devices 功能描述:DAC 1-CH Segment 14-bit 48-Pin LQFP T/R |
| AD9772AASTZ | 功能描述:IC DAC 14BIT 160MSPS 48-LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC+® 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 設(shè)置時(shí)間:4µs 位數(shù):12 數(shù)據(jù)接口:串行 轉(zhuǎn)換器數(shù)目:2 電壓電源:單電源 功率耗散（最大）:- 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:8-TSSOP，8-MSOP（0.118"，3.00mm 寬） 供應(yīng)商設(shè)備封裝:8-uMAX 包裝:管件 輸出數(shù)目和類型:2 電壓，單極 采樣率（每秒）:* 產(chǎn)品目錄頁面:1398 (CN2011-ZH PDF) |
| AD9772AASTZRL | 功能描述:IC DAC 14BIT 160MSPS 48LQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 數(shù)模轉(zhuǎn)換器 系列:TxDAC+® 產(chǎn)品培訓(xùn)模塊:Data Converter Fundamentals DAC Architectures 標(biāo)準(zhǔn)包裝:750 系列:- 設(shè)置時(shí)間:7µs 位數(shù):16 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 電壓電源:雙 ± 功率耗散（最大）:100mW 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:28-LCC（J 形引線） 供應(yīng)商設(shè)備封裝:28-PLCC（11.51x11.51） 包裝:帶卷 (TR) 輸出數(shù)目和類型:1 電壓，單極；1 電壓，雙極 采樣率（每秒）:143k |
| AD9772A-EB | 制造商:Analog Devices 功能描述:14 BIT DAC W/2X INTERPOLATION 制造商:Analog Devices 功能描述:DEV TOOLS, EVAL BD FOR AD9772A - Bulk |
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