參數(shù)資料
型號(hào)： AD9772A
廠(chǎng)商： Analog Devices, Inc.
英文描述： 14-Bit, 160 MSPS TxDAC+ with 2x Interpolation Filter
中文描述： 14位，160 MSPS的TxDAC系列的2倍插值濾波器
文件頁(yè)數(shù)： 19/32頁(yè)
文件大小： 596K
代理商： AD9772A
REV. A
AD9772A
–19–
AD9772A
CLK+
CLKVDD
CLK
–
CLKCOM
0.1 F
0.1 F
0.1 F
1k
1k
1k
1k
ECL/PECL
Figure 21. Differential Clock Interface
The quality of the clock and data input signals are important in
achieving the optimum performance. The external clock driver
circuitry should provide the AD9772A with a low jitter clock
input which meets the min/max logic levels while providing fast
edges. Although fast clock edges help minimize any jitter that
will manifest itself as phase noise on a reconstructed waveform,
the high gain-bandwidth product of the AD9772A
’
s differential
comparator can tolerate sine wave inputs as low as 0.5 V p-p,
with minimal degradation in its output noise floor.
Digital signal paths should be kept short and run lengths
matched to avoid propagation delay mismatch. The insertion of
a low- value resistor network (i.e., 50
to 200
) between the
AD9772A digital inputs and driver outputs may be helpful in
reducing any overshooting and ringing at the digital inputs that
contribute to data feedthrough.
SLEEP MODE OPERATION
The AD9772A has a SLEEP function that turns off the output
current and reduces the analog supply current to less than 6 mA
over the specified supply range of 2.8 V to 3.2 V. This mode
can be activated by applying a Logic Level 1 to the SLEEP
pin. The AD9772A takes less than 50 ns to power down and
approximately 15
μ
s to power back up.
POWER DISSIPATION
The power dissipation, P
D
, of the AD9772A is dependent on
several factors, including:
1. AVDD, PLLVDD, CLKVDD, and DVDD, the power sup-
ply voltages.
2. I
OUTFS
, the full-scale current output.
3. f
DATA
, the update rate.
4. the reconstructed digital input waveform.
The power dissipation is directly proportional to the analog
supply current, I
AVDD
, and the digital supply current, I
DVDD
.
I
AVDD
is directly proportional to I
OUTFS,
and is insensitive
to f
DATA
.
Conversely, I
DVDD
is dependent on both the digital input
waveform and f
DATA
. Figure 22 shows I
DVDD
as a function of
full-scale sine wave output ratios (f
OUT
/f
DATA
) for various update
rates with DVDD = 3 V. The supply current from CLKVDD
and PLLVDD is relatively insensitive to the digital input wave-
form, but shown directly proportional to the update rate as
shown in Figure 23.
RATIO
–
f
OUT
/
f
DATA
100
90
40
0.0
D
–
80
70
60
50
0.1
0.2
0.3
0.4
0.5
30
20
10
0
f
DATA
= 160MSPS
f
DATA
= 125MSPS
f
DATA
= 100MSPS
f
DATA
= 65MSPS
f
DATA
= 50MSPS
f
DATA
= 25MSPS
Figure 22. I
DVDD
vs. Ratio @ DVDD = 3.3 V
f
DATA
–
MSPS
25
0
0
I
–
20
15
10
5
50
100
150
200
I
PLLVDD
I
CLKVDD
Figure 23. I
PLLVDD
and I
CLKVDD
vs. f
DATA
APPLYING THE AD9772A OUTPUT CONFIGURATIONS
The following sections illustrate some typical output configura-
tions for the AD9772A. Unless otherwise noted, it is assumed
that I
OUTFS
is set to a nominal 20 mA for optimum performance.
For applications requiring the optimum dynamic performance,
a differential output configuration is highly recommended. A
differential output configuration may consist of either an RF
transformer or a differential op amp configuration. The trans-
former configuration provides the optimum high-frequency
performance and is recommended for any application allowing
for ac coupling. The differential op amp configuration is suitable
for applications requiring dc coupling, a bipolar output, signal
gain, and/or level-shifting.
A single-ended output is suitable for applications requiring a
unipolar voltage output. A positive unipolar output voltage will
result if I
OUTA
and/or I
OUTB
is connected to an appropriately-sized
load resistor, R
LOAD
, referred to ACOM. This configuration may
be more suitable for a single-supply system requiring a dc-coupled,
ground-referred output voltage. Alternatively, an amplifier could
be configured as an I-V converter, thus converting I
OUTA
or
I
OUTB
into a negative unipolar voltage. This configuration pro-
vides the best dc linearity since I
OUTA
or I
OUTB
is maintained at
a virtual ground.
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