參數(shù)資料
型號(hào)： AD9547BCPZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 57/104頁(yè)
文件大?。?/td> 0K
描述： IC CLOCK GEN/SYNCHRONIZR 64LFCSP
產(chǎn)品變化通告： AD9547 Mask Change 20/Oct/2010
標(biāo)準(zhǔn)包裝： 1
類型： 時(shí)鐘/頻率發(fā)生器，同步器
PLL： 是
主要目的： 以太網(wǎng)，SONET/SDH，Stratum
輸入： CMOS，LVDS，LVPECL
輸出： CMOS，LVDS，LVPECL
電路數(shù)： 1
比率 - 輸入:輸出： 2:2
差分 - 輸入:輸出： 是/是
頻率 - 最大： 750kHz
電源電壓： 1.71 V ~ 3.465 V
工作溫度： -40°C ~ 85°C
安裝類型： 表面貼裝
封裝/外殼： 64-VFQFN 裸露焊盤，CSP
供應(yīng)商設(shè)備封裝： 64-LFCSP-VQ（9x9）
包裝： 托盤
AD9547
Data Sheet
Rev. E | Page 56 of 104
Data Transfer Process
The master initiates data transfer by asserting a start condition.
This indicates that a data stream follows. All I2C slave devices
connected to the serial bus respond to the start condition.
The master then sends an 8-bit address byte over the SDA line,
consisting of a 7-bit slave address (MSB first) plus an R/W bit.
This bit determines the direction of the data transfer, that is,
whether data is written to or read from the slave device (0 =
write, 1 = read).
The peripheral whose address corresponds to the transmitted
address responds by sending an acknowledge bit. All other devices
on the bus remain idle while the selected device waits for data to be
read from or written to it. If the R/W bit = 0, the master (trans-
mitter) writes to the slave device (receiver). If the R/W bit = 1,
the master (receiver) reads from the slave device (transmitter).
See the Data Transfer Format section for the command format.
Data is then sent over the serial bus in the format of nine clock
pulses, one data byte (eight bits) from either master (write mode)
or slave (read mode) followed by an acknowledge bit from the
receiving device. The number of bytes that can be transmitted
per transfer is unrestricted. In write mode, the first two data
bytes immediately after the slave address byte are the internal
memory (control registers) address bytes with the high address
byte first. This addressing scheme gives a memory address up to
216 1 = 65,535. The data bytes after these two memory address
bytes are register data written into or read from the control regi-
sters. In read mode, the data bytes after the slave address byte are
register data written into or read from the control registers.
When all data bytes are read or written, stop conditions are estab-
lished. In write mode, the master (transmitter) asserts a stop
condition to end data transfer during the 10th clock pulse following
the acknowledge bit for the last data byte from the slave device
(receiver). In read mode, the master device (receiver) receives the
last data byte from the slave device (transmitter) but does not pull
SDA low during the ninth clock pulse. This is known as a no
acknowledge bit. When receiving the no acknowledge bit, the slave
device knows the data transfer is finished and enters idle mode.
The master then takes the data line low during the low period
before the 10th clock pulse, and high during the 10th clock pulse
to assert a stop condition.
A start condition can be used in place of a stop condition.
Furthermore, a start or stop condition can occur at any time,
and partially transferred bytes are discarded.
12
89
12
3 TO 7
89
10
ACK FROM
SLAVE RECEIVER
ACK FROM
SLAVE RECEIVER
SDA
SCL
S
MSB
P
08
30
0-
0
38
Figure 62. Data Transfer Process (Master Write Mode, 2-Byte Transfer Used for Illustration)
12
89
12
3 TO 7
89
10
ACK FROM
MASTER RECEIVER
NO ACK FROM
MASTER RECEIVER
SDA
SCL
S
P
08
30
0-
03
9
Figure 63. Data Transfer Process (Master Read Mode, 2-Byte Transfer Used for Illustration)
Data Transfer Format
In write byte format, the write byte protocol is used to write a register address to the RAM starting from the specified RAM address.
S
Slave
Address
W
A
RAM Address
High Byte
A
RAM Address
Low Byte
A
RAM
Data 0
A
RAM
Data 1
A
RAM
Data 2
A
P
In send byte format, the send byte protocol is used to set up the register address for subsequent reads.
S
Slave Address
W
A
RAM Address High Byte
A
RAM Address Low Byte
A
P
In receive byte format, the receive byte protocol is used to read the data bytes from RAM starting from the current address.
S
Slave Address
R
A
RAM Data 0
A
RAM Data 1
A
RAM Data 2
A
P
Read byte format combines the format of the send byte and the receive byte formats.
S
Slave
Address
W
A
RAM
Address
High Byte
A
RAM
Address
Low Byte
A
Sr
Slave
Address
R
A
RAM
Data
0
A
RAM
Data
1
A
RAM
Data
2
A
P
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