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參數(shù)資料
| 型號： | AD9547BCPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 36/104頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC CLOCK GEN/SYNCHRONIZR 64LFCSP |
| 產品變化通告： | AD9547 Mask Change 20/Oct/2010 |
| 標準包裝： | 1 |
| 類型： | 時鐘/頻率發(fā)生器，同步器 |
| PLL： | 是 |
| 主要目的： | 以太網(wǎng)，SONET/SDH，Stratum |
| 輸入： | CMOS，LVDS，LVPECL |
| 輸出： | CMOS，LVDS，LVPECL |
| 電路數(shù)： | 1 |
| 比率 - 輸入:輸出： | 2:2 |
| 差分 - 輸入:輸出： | 是/是 |
| 頻率 - 最大： | 750kHz |
| 電源電壓： | 1.71 V ~ 3.465 V |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 64-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 64-LFCSP-VQ（9x9） |
| 包裝： | 托盤 |
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Data Sheet
AD9547
Rev. E | Page 37 of 104
RecoveryfromHoldover
When in holdover, if a valid reference becomes available, the
device exits holdover operation. The loop state machine restores
the DPLL to closed-loop operation, locks tothe selected reference,
and sequences the recovery of all the loop parameters based on
the profile settings for the active reference.
Note that if the user holdover bit (Register 0x0A01, Bit 6) is set,
the device does not automatically exit holdover when a valid
reference is available. However, automatic recovery can occur
after clearing the user holdover bit.
SYSTEM CLOCK INPUTS
Functional Description
The system clock circuit provides a low jitter, stable, high fre-
quency clock for use by the rest of the chip. The user has the
option of directly driving the SYSCLKx inputs with a high
frequency clock source at the desired system clock rate.
Alternatively, the SYSCLKx input can be configured to operate
in conjunction with the internal SYSCLK PLL. The SYSCLK
PLL can synthesize the system clock by means of a crystal
resonator connected across the SYSCLKx input pins or by
means of direct application of a low frequency clock source.
The SYSCLKx inputs are internally biased toa dc levelof ~1 V.
Take care to ensure that any external connections do not disturb
the dc bias because such a disturbance can significantly degrade
performance. Generally, the SYSCLKx inputs should be ac-coupled
to the signal source (except when using a crystal resonator).
Low Loop Bandwidth Applications UsingaTCXO/OCXO
For many applications, the use of a crystal oscillator is a cost-
effective and simple choice. The stability is good enough to
support loop bandwidths down to 50 Hz, and the holdover
performance is good enough for all except the most demanding
applications.
In cases where Stratum 2 or Stratum 3 holdover performance is
needed, or in cases where the loop bandwidth must be <50 Hz,
either a TCXO or OCXO must be used. If the loop bandwidths
are lower than 10 millihertz, an OCXO must be used. Choose a
TCXO/OCXOwith a high output frequency and CMOS output to
achieve the best performance. AN-1079 Application Note,
Determining the Maximum Tolerable Frequency Drift Rate of the
AD9548 System Clock in Low Loop BandwidthApplications
discusses systemclock performance considerations for lowloop
bandwidth applications.
When interfacing the TCXO/OCXO, a voltage divider on the
output should be used to reduce the voltage swing to 1 V p-p,
and that signal should be ac-coupled to the SYSCLKP pin.
The SYSCLKN pin can be bypassed to ground with a 0.01 F
capacitor.
Choosingthe SystemClock OscillatorFrequency
The best performance of the AD9548 is achieved when the
system clock is not an integer multiple of the DDS output
frequency.
As an example, using a 19.44 MHz oscillator for the systemclock
in a 156.25 MHz Ethernet application yields better performance
than a 25 MHz oscillator.
Another good systemclock choice for many communications
applications is a49.152 MHz crystal used in IEEE1394 (FireWire)
because nearly all output frequencies are not integer related to this
frequency and the crystalis readily available.
SystemClock Details
A block diagramof the systemclock appears in Figure 44. The
signal at the SYSCLKx input pins becomes the internally buffered
DAC sampling clock (fS) via one of three paths.
High frequency direct (HF)
Low frequency synthesized (LF)
Crystal resonator synthesized (XTAL)
Note that both the LF and XTAL paths require the use of the
SYSCLK PLL (see the SYSCLK PLL Multiplier section).
The main purpose of the HF path is to allow the direct use of
a high frequency (500 MHz to 1 GHz) external clock source for
clocking the AD9547. This path is optimized for high frequency
and low noise floor. Note that the HF input also provides a path
to SYSCLK PLL (see the SYSCLK PLL Multiplier section), which
includes an input divider (M) programmable for divide-by 1,
2, 4, or 8. The purpose of the divider is to limit the frequency
at the input to the PLL to less than 150 MHz, which is the maxi-
mum PFD rate.
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| AD9547BCPZ-REEL7 | 功能描述:IC CLOCK GEN/SYNCHRONIZR 64LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:28 系列:- 類型:時鐘/頻率發(fā)生器 PLL:是 主要目的:Intel CPU 服務器 輸入:時鐘 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:3:22 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3.135 V ~ 3.465 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:64-TFSOP （0.240"，6.10mm 寬） 供應商設備封裝:64-TSSOP 包裝:管件 |
| AD9548 | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad/Octal Input Network Clock Generator/Synchronizer |
| AD9548/PCBZ | 功能描述:BOARD EVAL FOR AD9548 RoHS:是 類別:編程器，開發(fā)系統(tǒng) >> 評估演示板和套件 系列:- 標準包裝:1 系列:PSoC® 主要目的:電源管理，熱管理 嵌入式:- 已用 IC / 零件:- 主要屬性:- 次要屬性:- 已供物品:板，CD，電源 |
| AD9548/PCBZ | 制造商:Analog Devices 功能描述:Clock Generator Evaluation Board |
| AD9548BCPZ | 功能描述:IC CLOCK GEN/SYNCHRONIZR 88LFCSP RoHS:是 類別:集成電路 (IC) >> 時鐘/計時 - 專用 系列:- 標準包裝:1 系列:- 類型:時鐘/頻率發(fā)生器，多路復用器 PLL:是 主要目的:存儲器，RDRAM 輸入:晶體 輸出:LVCMOS 電路數(shù):1 比率 - 輸入:輸出:1:2 差分 - 輸入:輸出:無/是 頻率 - 最大:400MHz 電源電壓:3 V ~ 3.6 V 工作溫度:0°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:Digi-Reel® 其它名稱:296-6719-6 |
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