參數(shù)資料
型號(hào)： AD9430
廠(chǎng)商： Analog Devices, Inc.
英文描述： 12-Bit, 170 MSPS 3.3V A/D Converter
中文描述： 12位，170 MSPS的3.3VA / D轉(zhuǎn)換器
文件頁(yè)數(shù)： 9/20頁(yè)
文件大?。?/td> 1594K
代理商： AD9430
PRELIMINARY TECHNICAL DATA
AD9430
REV. PrG 4/01/2002 -9-
PIN FUNCTION DESCRIPTIONS (LVDS mode )
LVDS Mode
Pin Number
2,42,43,44,45,46
1
Name
Function in LVDS Mode
DNC
S5
Do not connect
Full Scale Adjust pin : ‘1’ sets FS =
.766 V
pp differential,
‘0’ sets FS =
1.533 V
pp differential
Interlaced or parallel output mode. (only in Dual Port mode
operation) HIGH = data arrives in channel A at falling edge of clock
and data arrives in channelA at rising edge of clock. LOW = data
arrives in channels A and B at rising edge of clock.
Output Mode select. Low = Dual Port, CMOS; High = LVDS
Data format select. Low = Binary, High = Two’s compliment
Sets LVDS Output Current = 3.5mA
(Place 3.7K RSET resistor from LVDSBIAS to ground)
3.3V analog supply. (3.0V to 3.6V)
3
S4
5
6
7
S2
S1
LVDSBIAS
8,14,15,18,19,24,27,28,29,34,
39,40,88,89,90,94,95,98,99
4,9,12,13,16,17,20,23,25,26,3
0,31,35,38,41,86,87,91,92,93,
96,97,100
10
11
21
22
32
33
36
37
47,54,62,75,83
AV
DD
AGND
Analog Ground
SENSE
VREF
VIN+
VIN-
DS+
DS-
ENC+
ENC-
DrV
DD
Control Pin for Reference , Full Scale
1.235 Reference I/O - function dependent on REFSENSE
Analog input – true.
Analog input – compliment.
Data sync (input) – Not used in LVDS mode.Tie LOW .
Data sync (input) – compliment. Not used in LVDS mode.Tie HIGH.
Clock input – true. (LVPECL levels)
Clock input – compliment. (LVPECL levels)
3.3V digital output supply.
48,53,61,67,74,82
49
50
51
52
55
56
57
58
59
60
63
64
65
66
68
69
70
71
72
73
76
77
78
79
80
81
84
85
DrGND
D0_C
D0_T
D1_C
D1_T
D2_C
D2_T
D3_C
D3_T
D4_C
D4_T
DCO-
DCO+
D5_C
D5_T
D6_C
D6_T
D7_C
D7_T
D8_C
D8_T
D9_C
D9_T
D10_C
D10_T
D11_C
D11_T
OR_C
OR_T
Digital ground.
D0 complement output bit (LSB) (LVDS Levels)
D0 true output bit (LSB) (LVDS Levels)
D1 complement output bit (LVDS Levels)
D1 true output bit (LVDS Levels)
D2 complement output bit (LVDS Levels)
D2 true output bit (LVDS Levels)
D3 complement output bit (LVDS Levels)
D3 true output bit (LVDS Levels)
D4 complement output bit (LVDS Levels)
D4 true output bit (LVDS Levels)
Data Clock output – compliment. (LVDS Levels)
Data Clock output – true. (LVDS Levels)
D5 complement output bit (LVDS Levels)
D5 true output bit (LVDS Levels)
D6 complement output bit (LVDS Levels)
D6 true output bit (LVDS Levels)
D7 complement output bit (LVDS Levels)
D7 true output bit (LVDS Levels)
D8 complement output bit (LVDS Levels)
D8 true output bit (LVDS Levels)
D9 complement output bit (LVDS Levels)
D9 true output bit (LVDS Levels)
D10 complement output bit (LVDS Levels)
D10 true output bit (LVDS Levels)
D11 complement output bit (LVDS Levels) MSB
D11 true output bit (LVDS Levels) MSB
Overrange complement output bit (LVDS Levels)
Overrange true output bit (LVDS Levels)
相關(guān)PDF資料
PDF描述
AD9430BSV-170 12-Bit, 170 MSPS 3.3V A/D Converter
AD9432BST-80 12-Bit, 80 MSPS/105 MSPS A/D Converter
AD9432BST-105 12-Bit, 80 MSPS/105 MSPS A/D Converter
AD9432BSQ-105 12-Bit, 80 MSPS/105 MSPS A/D Converter
AD9432BSQ-80 12-Bit, 80 MSPS/105 MSPS A/D Converter
相關(guān)代理商/技術(shù)參數(shù)
參數(shù)描述
AD9430/PCB-CMOS 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:12-Bit, 170 MSPS 3.3V A/D Converter
AD9430_10 制造商:AD 制造商全稱(chēng):Analog Devices 功能描述:12-Bit, 170/210 MSPS 3.3 V A/D Converter
AD9430BSV-170 制造商:Analog Devices 功能描述:ADC Single Pipelined 170Msps 12-bit Parallel 100-Pin TQFP EP 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述:IC 12-BIT ADC
AD9430BSV-210 制造商:Analog Devices 功能描述:ADC Single Pipelined 210Msps 12-bit Parallel 100-Pin TQFP EP 制造商:Analog Devices 功能描述:IC ADC 12BIT 210MSPS TQFP-100
AD9430BSV-270 制造商:Analog Devices 功能描述:12 BIT 170 MSPS ADC - Bulk
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