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參數(shù)資料
| 型號： | AD9430 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit, 170 MSPS 3.3V A/D Converter |
| 中文描述： | 12位，170 MSPS的3.3VA / D轉換器 |
| 文件頁數(shù)： | 12/20頁 |
| 文件大?。?/td> | 1594K |
| 代理商： | AD9430 |
PRELIMINARY TECHNICAL DATA
AD9430
APPLICATION NOTES
THEORY OF OPERATION
The AD9430 architecture is optimized for high speed and
ease of use. The analog inputs drive an integrated high
bandwidth track-and-hold circuit that samples the signal
prior to quantization by the 12-bit core. For ease of use the
part includes an onboard reference and input logic that
accepts TTL, CMOS, or LVPECL levels. The digital outputs
logic levels are user selectable as standard 3V CMOS or
LVDS (ANSI-644 compatible) via pin S2.
USING THE AD9430
ENCODE Input
Any high speed A/D converter is extremely sensitive to the
quality of the sampling clock provided by the user. A
track/hold circuit is essentially a mixer, and any noise,
distortion, or timing jitter on the clock will be combined
with the desired signal at the A/D output. For that reason,
considerable care has been taken in the design of the
ENCODE input of the AD9430, and the user is advised to
give commensurate thought to the clock source.
The AD9430 has an internal clock duty cycle stabilization
circuit that locks to the rising edge of ENCODE (falling
edge of ENCODE if driven differentially), and optimizes
timing internally. This allows for a wide range of input duty
cycles at the input without degrading performance. Jitter in
the rising edge of the input is still of paramount concern, and
is not reduced by the internal stabilization circuit. This
circuit is always on, and cannot be disabled by the user.
The ENCODE and ENCODE inputs are internally biased to
1.5V (nominal), and support either differential or single –
ended signals. For best dynamic performance, a differential
signal is recommended. Good performance is obtained
using an MC10EL16 in the circuit to drive the
encode inputs , as illustrated in figure below.
-12- 4/01/2002 REV. PrG
Driving Encode with EL16
Analog Input
The analog input to the AD9430 is a differential buffer. For
best dynamic performance, impedances at
AIN
and
should match. The analog input has been optimized to
provide superior wideband performance and requires that the
analog inputs be driven differentially. SNR and SINAD
performance will degrade significantly (~6dB) if the analog
input is driven with a single-ended signal. A wideband
transformer such as Minicircuits ADT1-1WT can be used to
provide the
____
AIN
differential analog inputs for applications that require a
single-ended-to-differential conversion. Both analog inputs
are self-biased by an on-chip resistor divider to a nominal
2.8 V. (See Equivalent Circuits section TBD.)
Special care was taken in the design of the Analog Input
section of the AD9430 to prevent damage and corruption of
data when the input is overdriven. The nominal input range
is 1.5 V diff p-p. The nominal differential input range is 768
mV p-p × 2.
Differential Analog Input Range
Single Ended Analog Input Range
相關PDF資料 |
PDF描述 |
|---|---|
| AD9430BSV-170 | 12-Bit, 170 MSPS 3.3V A/D Converter |
| AD9432BST-80 | 12-Bit, 80 MSPS/105 MSPS A/D Converter |
| AD9432BST-105 | 12-Bit, 80 MSPS/105 MSPS A/D Converter |
| AD9432BSQ-105 | 12-Bit, 80 MSPS/105 MSPS A/D Converter |
| AD9432BSQ-80 | 12-Bit, 80 MSPS/105 MSPS A/D Converter |
相關代理商/技術參數(shù) |
參數(shù)描述 |
|---|---|
| AD9430/PCB-CMOS | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 170 MSPS 3.3V A/D Converter |
| AD9430_10 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 170/210 MSPS 3.3 V A/D Converter |
| AD9430BSV-170 | 制造商:Analog Devices 功能描述:ADC Single Pipelined 170Msps 12-bit Parallel 100-Pin TQFP EP 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述:IC 12-BIT ADC |
| AD9430BSV-210 | 制造商:Analog Devices 功能描述:ADC Single Pipelined 210Msps 12-bit Parallel 100-Pin TQFP EP 制造商:Analog Devices 功能描述:IC ADC 12BIT 210MSPS TQFP-100 |
| AD9430BSV-270 | 制造商:Analog Devices 功能描述:12 BIT 170 MSPS ADC - Bulk |
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