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參數(shù)資料
| 型號： | AD9430 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | 12-Bit, 170 MSPS 3.3V A/D Converter |
| 中文描述： | 12位，170 MSPS的3.3VA / D轉(zhuǎn)換器 |
| 文件頁數(shù)： | 10/20頁 |
| 文件大小： | 1594K |
| 代理商： | AD9430 |
PRELIMINARY TECHNICAL DATA
AD9430
TERMINOLOGY
Analog Bandwidth
The analog input frequency at which the spectral power of
the fundamental frequency (as determined by the FFT
analysis) is reduced by 3 dB.
Aperture Delay
The delay between the 50% point of the rising edge of the
ENCODE command and the instant at which the analog
input is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Crosstalk
Coupling onto one channel being driven by a low level (–40
dBFS) signal when the adjacent interfering channel is driven
by a full-scale signal.
Differential Analog Input Resistance, Differential Analog
Input Capacitance and Differential Analog Input
Impedance
The real and complex impedances measured at each analog
input port. The resistance is measured statically and the
capacitance and differential input impedances are measured
with a network analyzer.
Differential Analog Input Voltage Range
The peak-to-peak differential voltage that must be applied to
the converter to generate a full-scale response. Peak
differential voltage is computed by observing the voltage on
a single pin and subtracting the voltage from the other pin,
which is 180 degrees out of phase. Peak-to-peak differential
is computed by rotating the inputs phase 180 degrees and
again taking the peak measurement. The difference is then
computed between both peak measurements.
Differential Nonlinearity
The deviation of any code width from an ideal 1 LSB step.
Effective Number of Bits
The effective number of bits (ENOB) is calculated from the
measured SNR based on the equation:
SNR
ENOB
=
-10- 4/01/2002 REV. PrG
02
.
76
.
dB
MEASURED
ENCODE Pulsewidth / Duty Cycle
Pulsewidth high is the minimum amount of time that the
ENCODE pulse should be left in Logic 1 state to achieve
rated performance; pulsewidth low is the minimum time
ENCODE pulse should be left in low state. See timing
implications of changing t
ENCH
in text. At a given clock rate,
these specifica-tions define an acceptable ENCODE duty
cycle.
Full-Scale Input Power
Expressed in dBm. Computed using the following equation:
Fullscale
Z
Power
=
001
.
log
10
2
Input
Fullscale
V
rms
Gain Error
Gain error is the difference between the measured and ideal
full scale input voltage range of the ADC.
Harmonic Distortion, Second
The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.
Harmonic Distortion, Third
The ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBc.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line”
determined by a least square curve fit.
Minimum Conversion Rate
The encode rate at which the SNR of the lowest analog
signal frequency drops by no more than 3 dB below the
guaranteed limit.
Maximum Conversion Rate
The encode rate at which parametric testing is performed.
Output Propagation Delay
The delay between a differential crossing of ENCODE and
ENCODE and the time when all output data bits are within
valid logic levels.
Noise (for Any Range within the ADC)
=
10
10
*
001
.
dBFS
dBc
dBm
Signal
SNR
FS
noise
Where
Z
is the input impedance,
FS
is the full scale of the
device for the frequency in question,
SNR
is the value for the
particular input level, and
Signal
is the signal level within
the ADC reported in dB below full scale. This value includes
both thermal and quantization noise.
Power Supply Rejection Ratio
The ratio of a change in input offset voltage to a change in
power supply voltage.
Signal-to-Noise-and-Distortion (SINAD)
The ratio of the rms signal amplitude (set 1 dB below full
scale) to the rms value of the sum of all other spectral
components, including harmonics but excluding dc.
Z
V
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9430BSV-170 | 12-Bit, 170 MSPS 3.3V A/D Converter |
| AD9432BST-80 | 12-Bit, 80 MSPS/105 MSPS A/D Converter |
| AD9432BST-105 | 12-Bit, 80 MSPS/105 MSPS A/D Converter |
| AD9432BSQ-105 | 12-Bit, 80 MSPS/105 MSPS A/D Converter |
| AD9432BSQ-80 | 12-Bit, 80 MSPS/105 MSPS A/D Converter |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9430/PCB-CMOS | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 170 MSPS 3.3V A/D Converter |
| AD9430_10 | 制造商:AD 制造商全稱:Analog Devices 功能描述:12-Bit, 170/210 MSPS 3.3 V A/D Converter |
| AD9430BSV-170 | 制造商:Analog Devices 功能描述:ADC Single Pipelined 170Msps 12-bit Parallel 100-Pin TQFP EP 制造商:Rochester Electronics LLC 功能描述:- Bulk 制造商:Analog Devices 功能描述:IC 12-BIT ADC |
| AD9430BSV-210 | 制造商:Analog Devices 功能描述:ADC Single Pipelined 210Msps 12-bit Parallel 100-Pin TQFP EP 制造商:Analog Devices 功能描述:IC ADC 12BIT 210MSPS TQFP-100 |
| AD9430BSV-270 | 制造商:Analog Devices 功能描述:12 BIT 170 MSPS ADC - Bulk |
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