- 您現(xiàn)在的位置：買賣IC網(wǎng) > PDF目錄373962 > AD9289 (Analog Devices, Inc.) Quad 8-Bit, 65 MSPS Serial LVDS 3V A/D Converter PDF資料下載
參數(shù)資料
| 型號(hào)： | AD9289 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Quad 8-Bit, 65 MSPS Serial LVDS 3V A/D Converter |
| 中文描述： | 四8位，65 MSPS的串行LVDS 3V的A / D轉(zhuǎn)換 |
| 文件頁數(shù)： | 9/16頁 |
| 文件大?。?/td> | 1376K |
| 代理商： | AD9289 |
Prelimnary Technical Data
AD9289
THEORY OF OPERATION
Rev. PrJ | Page 9 of 16
6/25/2004
Each A/D converter in the AD9289 architecture consists of a front-
end sample and hold amplifier (SHA) followed by a pipelined
switched capacitor A/D converter. The pipelined A/D converter is
divided into two sections, consisting of six 1.5-bit stages and a
final 3-bit flash. Each stage provides sufficient overlap to correct
for flash errors in the preceding stages. The quantized outputs from
each stage are combined into a final 8-bit result in the digital
correction logic. The pipelined architecture permits the first stage
to operate on a new input sample while the remaining stages
operate on preceding samples. Sampling occurs on the rising edge
of the clock.
Each stage of the pipeline, excluding the last, consists of a low
resolution flash A/D connected to a switched capacitor DAC and
interstage residue amplifier (MDAC). The residue amplifier
magnifies the difference between the reconstructed DAC output
and the flash input for the next stage in the pipeline. One bit of
redundancy is used in each one of the stages to facilitate digital
correction of flash errors. The last stage simply consists of a flash
A/D.
The input stage contains a differential SHA that can be configured
as ac- or dc-coupled in differential or single-ended modes. The
output-staging block aligns the data, carries out the error correction
and passes the data to the output buffers.During power-down the
output buffers go into a high-impedance state.
Clock Input
Typical high-speed A/D converters use both clock edges to
generate a variety of internal timing signals, and as a result may be
sensitive to clock duty cycle. Commonly a +/-5% tolerance is
required on the clock duty cycle to maintain dynamic performance
characteristics. The AD9289 contains a clock duty cycle stabilizer
that retimes the non-sampling edge, providing an internal clock
signal with a nominal 50% duty cycle. This allows a wide range of
clock input duty cycles without affecting the performance of the
AD9289. As shown in TPC XX, noise and distortion performance
are nearly flat over at least a +/-15% range of duty cycle. The
stabilizer circuit can be bypassed by grounding input pin DCR. (
There is an internal 22K ohm pull-up resistor)
The duty cycle stabilizer uses a delay-locked loop (DLL) to create
the non-sampling edge. As a result, any changes to the sampling
frequency will require approximately 100 clock cycles to allow the
DLL to acquire and lock to the new rate. High-speed, high-
resolution A/Ds are sensitive to the quality of the clock input. The
degradation in SNR at a given full-scale input frequency (f
) due
only to aperture jitter (tA) can be calculated with the following
equation:
SNR degradation = 20 × log10 [1/2 × pi × fA
×
tA]
In the equation, the rms aperture jitter,
tA
, represents the root sum
square of all jitter sources, which include the clock input, analog
input signal, and A/D aperture jitter specification. Undersampling
applications are particularly sensitive to jitter.
The clock input should be treated as an analog signal in cases
where aperture jitter may affect the dynamic range of the AD9289.
Power supplies for clock drivers should be separated from the A/D
output driver supplies to avoid modulating the clock signal with
digitalnoise. Low jitter, crystal-controlled oscillators make the
best clock sources. If the clock is generated from another type of
source (by gating, dividing, or other methods), it should be retimed
by the original clock at the last step.
Analog Inputs
For best dynamic performance, the source impedances driving
VIN+ and VIN– should be matched such that common-mode
settling errors are symmetrical. These errors will be reduced by the
common-mode rejection of the A/D.
Voltage Reference
A stable and accurate 0.5 V voltage reference is built into the
AD9289. The input range can be adjusted by varying the reference
voltage applied to the AD9289, using either the internal reference
or an externally applied reference voltage. The input span of the
A/D tracks reference voltage changes linearly. The Shared
Reference mode allows the user to connect the references from the
quad ADC together externally for superior gain and offset
matching performance. If the ADCs are to function independently,
the reference decoupling can be treated independently and can
provide superior isolation between the four channels. To enable
Shared Reference mode, the SHARED_REF pin must be tied high
and external differential references must be externally shorted.
(REFT_A must be externally shorted to REFT_B and REFB_A
must be shorted to REFB_B.) Note that channels A and B are
referenced to REFT_A and REFB_A and channels C and D are
referenced to REFT_B and REFB_B.
Figure 3.
Shared Reference Mode
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| AD9289BBC-65 | Quad 8-Bit, 65 MSPS Serial LVDS 3V A/D Converter |
| AD9289BBC-65EB | Quad 8-Bit, 65 MSPS Serial LVDS 3V A/D Converter |
| AD9300 | 4 x 1 Wideband Video Multiplexer |
| AD9300KP | 4 x 1 Wideband Video Multiplexer |
| AD9300KQ | 4 x 1 Wideband Video Multiplexer |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| AD9289-65EB1 | 制造商:AD 制造商全稱:Analog Devices 功能描述:High Speed ADC USB FIFO Evaluation Kit |
| AD9289BBC | 功能描述:IC ADC 8BIT QUAD 65MSPS 64CSPBGA RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉(zhuǎn)換器 系列:- 標(biāo)準(zhǔn)包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉(zhuǎn)換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應(yīng)商設(shè)備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個(gè)單端，單極；1 個(gè)單端，雙極 |
| AD9289BBC-65 | 制造商:Analog Devices 功能描述:- Bulk |
| AD9289BBC-65EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad 8-Bit, 65 MSPS Serial LVDS 3V A/D Converter |
| AD9289BBCZ | 制造商:Analog Devices 功能描述:ADC Quad Pipelined 65Msps 8-bit Serial 64-Pin CSP-BGA |
發(fā)布緊急采購，3分鐘左右您將得到回復(fù)。