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參數(shù)資料
| 型號： | AD9289 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Quad 8-Bit, 65 MSPS Serial LVDS 3V A/D Converter |
| 中文描述： | 四8位，65 MSPS的串行LVDS 3V的A / D轉換 |
| 文件頁數(shù)： | 4/16頁 |
| 文件大?。?/td> | 1376K |
| 代理商： | AD9289 |
AD9289 Prelimnary Technical Data
DIGITAL SPECIFICATIONS
Rev. PrJ | Page 4 of 16
6/25/2004
AVDD = 3.0V, DRVDD = 3.0V
Parameter
Temp
Test
Level
Min
Typ
Max
Unit
Differential Input Voltage
1
Input Common Mode Voltage
Input Resistance
Input Capacitance
Logic ‘1’ Voltage
Logic ‘0’ Voltage
Input Resistance
Input Capacitance
Differential Output Voltage (V
OD
)
Output Offset Voltage (V
OS
)
Output Coding
Full
Full
Full
25
°
C
Full
Full
Full
Full
Full
Full
Full
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
IV
247
2.0
247
1.125
Twos Complement or
Binary
mVpp
V
k
pF
V
V
k
PF
mV
V
1.25
30
4
CLOCK INPUTS
(CLK+, CLK-)
0.8
454
1.375
LOGIC INPUTS
DIGITAL OUTPUTS
(LVDS Mode)
Table 2: Digital Specifications
AC SPECIFICATIONS
2
AVDD = 3.0 V, DRVDD = 3.0 V; INTERNAL REF; DIFFERENTIAL ANALOG AND CLOCK INPUT, LVDS OUTPUT
MODE
Parameter
Temp
Test
Level
Min
Typ
Max
Unit
f
IN
= 10.3 MHz
f
IN
= 19.6 MHz
f
IN
= 32.5 MHz
f
IN
= 51 MHz
f
IN
= 10.3 MHz
f
IN
= 19.6 MHz
f
IN
= 32.5 MHz
f
IN
= 51 MHz
f
IN
= 10.3 MHz
f
IN
= 19.6 MHz
f
IN
= 32.5 MHz
f
IN
= 51 MHz
f
IN
= 10.3 MHz
f
IN
= 19.6 MHz
f
IN
= 32.5 MHz
f
IN
= 51 MHz
f
IN
= 10.3 MHz
f
IN
= 19.6 MHz
f
IN
= 32.5 MHz
f
IN
= 51 MHz
f
IN
= 10.3 MHz
f
IN
= 19.6 MHz
f
IN
= 32.5 MHz
f
IN
= 51 MHz
25
°
C
25
°
C
25
°
C
25
°
C
25
°
C
25
°
C
25
°
C
25
°
C
25
°
C
25
°
C
25
°
C
25
°
C
25
°
C
25
°
C
25
°
C
25
°
C
25
°
C
25
°
C
25
°
C
25
°
C
25
°
C
25
°
C
25
°
C
25
°
C
V
V
I
V
V
V
I
V
V
V
I
V
V
V
I
V
V
V
I
V
V
V
I
V
47.5
47.5
47
47
7.5
7.5
62
59
62
59
60
58
dB
dB
dB
dB
dB
dB
dB
dB
Bits
Bits
Bits
Bits
dB
dB
dB
dB
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
SIGNAL TO NOISE
RATIO (SNR) –
Without Harmonics
SIGNAL TO NOISE
RATIO (SINAD) –
With Harmonics
EFFECTIVE
NUMBER OF BITS
(ENOB)
SPURIOUS FREE
DYNAMIC RANGE
(SFDR)
SECOND AND
THIRD HARMONIC
DISTORTION
TOTAL HARMONIC
DISTORTION (THD)
1
Clock Inputs are LVDS compatible .Clock Inputs require external DC bias and cannot be AC coupled.
2
SNR/harmonics based on an analog input voltage of –0.5 dBFS referenced to a 1 Vpp full-scale input range.
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