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參數(shù)資料
| 型號： | AD9289 |
| 廠商： | Analog Devices, Inc. |
| 英文描述： | Quad 8-Bit, 65 MSPS Serial LVDS 3V A/D Converter |
| 中文描述： | 四8位，65 MSPS的串行LVDS 3V的A / D轉換 |
| 文件頁數(shù)： | 7/16頁 |
| 文件大?。?/td> | 1376K |
| 代理商： | AD9289 |
Prelimnary Technical Data
AD9289
DEFINITIONS
Rev. PrJ | Page 7 of 16
6/25/2004
ANALOG BANDWIDTH
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
APERTURE DELAY
The delay between the 50% point of the rising edge of the
ENCODE command and the instant at which the analog input is
sampled.
APERTURE UNCERTAINTY (JITTER)
The sample-to-sample variation in aperture delay.
CROSSTALK
Coupling onto one channel being driven by a low level (-40 dBFS)
signal when the adjacent interfering channel is driven by a full-
scale signal.
DIFFERENTIAL ANALOG INPUT RESISTANCE,
DIFFERENTIAL ANALOG INPUT CAPACITANCE,
AND DIFFERENTIAL ANALOG INPUT IMPEDANCE
The real and complex impedances measured at each analog input
port. The resistance is measured statically and the capacitance and
differential input impedances are measured with a network
analyzer.
DIFFERENTIAL ANALOG INPUT VOLTAGE RANGE
The peak to peak differential voltage that must be applied to the
converter to generate a full scale response. Peak differential
voltage is computed by observing the voltage on a single pin and
subtracting the voltage from the other pin, which is 180 degrees
out of phase. Peak to peak differential is computed by rotating the
inputs phase 180 degrees and taking the peak measurement again.
DIFFERENTIAL NONLINEARITY
The deviation of any code width from an ideal 1 LSB step.
EFFECTIVE NUMBER OF BITS
The effective number of bits (ENOB) is calculated from the
measured SNR based on the equation:
02
.
76
.
dB
SNR
ENOB
MEASURED
=
CLOCK PULSE WIDTH/DUTY CYCLE
Pulse width high is the minimum amount of time that the Clock
pulse (CLK+) should be left in logic “1” state to achieve rated
performance; pulse width low is the minimum time the clock pulse
should be left in low state. See timing implications of changing t
clk
in text. At a given clock rate, these specs define an acceptable
clock duty cycle.
FULL SCALE INPUT POWER
Expressed in dBm. Computed using the following equation:
=
001
.
log
10
2
Input
Fullscale
Z
Fullscale
V
Power
rms
GAIN ERROR
Gain error is the difference between the measured and ideal full
scale input voltage range of the worst ADC.
GAIN MATCHING
Expressed in %FSR. Computed using the following equation:
%
100
*
2
min
max
min
max
+
=
FSR
FSR
FSR
FSR
ng
GainMatchi
where FSR
is the most positive gain error of the ADCs and
FSR
min
is the most negative gain error of the ADCs.
HARMONIC DISTORTION, SECOND
The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.
HARMONIC DISTORTION, THIRD
The ratio of the rms signal amplitude to the rms value of the third
harmonic component, reported in dBc.
INTEGRAL NONLINEARITY
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line”
determined by a least square curve fit.
MINIMUM CONVERSION RATE
The encode rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed limit.
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| AD9289BBC | 功能描述:IC ADC 8BIT QUAD 65MSPS 64CSPBGA RoHS:否 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - 模數(shù)轉換器 系列:- 標準包裝:1,000 系列:- 位數(shù):12 采樣率（每秒）:300k 數(shù)據(jù)接口:并聯(lián) 轉換器數(shù)目:1 功率耗散（最大）:75mW 電壓電源:單電源 工作溫度:0°C ~ 70°C 安裝類型:表面貼裝 封裝/外殼:24-SOIC（0.295"，7.50mm 寬） 供應商設備封裝:24-SOIC 包裝:帶卷 (TR) 輸入數(shù)目和類型:1 個單端，單極；1 個單端，雙極 |
| AD9289BBC-65 | 制造商:Analog Devices 功能描述:- Bulk |
| AD9289BBC-65EB | 制造商:AD 制造商全稱:Analog Devices 功能描述:Quad 8-Bit, 65 MSPS Serial LVDS 3V A/D Converter |
| AD9289BBCZ | 制造商:Analog Devices 功能描述:ADC Quad Pipelined 65Msps 8-bit Serial 64-Pin CSP-BGA |
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