CS T/R SWITCH
參數(shù)資料
型號(hào)： AD9272-65EBZ
廠商： Analog Devices Inc
文件頁(yè)數(shù)： 15/44頁(yè)
文件大?。?/td> 0K
描述： BOARD EVAL AD9272
設(shè)計(jì)資源： Powering AD9272 with ADP5020 Switching Regulator PMU for Increased Efficiency (CN0135)
標(biāo)準(zhǔn)包裝： 1
ADC 的數(shù)量： 8
位數(shù)： 12
采樣率（每秒）： 65M
數(shù)據(jù)接口： 串行
輸入范圍： 733 mVpp
在以下條件下的電源（標(biāo)準(zhǔn)）： 1.69W @ 65MSPS
工作溫度： -40°C ~ 85°C
已用 IC / 零件： AD9272
已供物品： 板，電源
相關(guān)產(chǎn)品： AD9272BSVZRL-80-ND - IC ADC ASD OCTAL 80MSPS 100-TQFP
AD9272BSVZRL-65-ND - IC ADC ASD OCTAL 65MSPS 100-TQFP
AD9272BSVZRL-40-ND - IC ADC ASD OCTAL 40MSPS 100-TQFP
AD9272BSVZ-80-ND - IC ADC OCT 12BIT 80MSPS 100-TQFP
AD9272BSVZ-65-ND - IC ADC OCT 12BIT 65MSPS 100-TQFP
AD9272BSVZ-40-ND - IC ADC OCT 12BIT 40MSPS 100-TQFP
AD9272
Rev. C | Page 22 of 44
0
702
9-
0
71
LNA
LI-x
LG-x
LO-x
DOUTx+
DOUTx–
CS
T/R
SWITCH
CLG
CFB R
FB2
CSH
GAIN
INTERPOLATOR
LOSW-x
RFB1
SWITCH
ARRAY
gm
CWD[7:0]+
CWD[7:0]–
ATTENUATOR
–42dB TO 0dB
GA
IN
–
PIPELINE
ADC
SERIAL
LVDS
POSTAMP
GA
IN
+
AD9272
T
R
ANS
D
UCE
R
FILTER
21dB
24dB,
27dB,
30dB
15.6dB,
17.9dB,
21.3dB
Figure 37. Simplified Block Diagram of a Single Channel
CHANNEL OVERVIEW
Each channel contains both a TGC signal path and a CW Doppler
signal path. Common to both signal paths, the LNA provides user-
adjustable input impedance termination. The CW Doppler path
includes a transconductance amplifier and a crosspoint switch.
The TGC path includes a differential X-AMP VGA, an antialiasing
filter, and an ADC. Figure 37 shows a simplified block diagram
with external components.
The signal path is fully differential throughout to maximize signal
swing and reduce even-order distortion; however, the LNA is
designed to be driven from a single-ended signal source.
Low Noise Amplifier (LNA)
Good noise performance relies on a proprietary ultralow noise
LNA at the beginning of the signal chain, which minimizes the
noise contribution in the following VGA. Active impedance
control optimizes noise performance for applications that benefit
from input impedance matching.
A simplified schematic of the LNA is shown in Figure 38. LI-x is
capacitively coupled to the source. An on-chip bias generator
establishes dc input bias voltages of around 0.9 V and centers
the output common-mode levels at 1.5 V (AVDD2 divided by
2). A capacitor, CLG, of the same value as the input coupling
capacitor, CS, is connected from the LG-x pin to ground.
07
02
9-
10
1
LI-x
CS
CLG
CFB
CSH
LG-x
LO-x
LOSW-x
VCM
VO+
VO–
RFB1
RFB2
T/R
SWITCH
T
RANS
DUCE
R
Figure 38. Simplified LNA Schematic
The LNA supports differential output voltages as high as 4.4 V p-p
with positive and negative excursions of ±1.1 V from a common-
mode voltage of 1.5 V. The LNA differential gain sets the maximum
input signal before saturation. One of three gains is set through
the SPI. The corresponding full-scale input for the gain settings
of 6, 8, and 12 is 733 mV p-p, 550 mV p-p, and 367 mV p-p,
respectively. Overload protection ensures quick recovery time
from large input voltages. Because the inputs are capacitively
coupled to a bias voltage near midsupply, very large inputs can
be handled without interacting with the ESD protection.
Low value feedback resistors and the current-driving capability
of the output stage allow the LNA to achieve a low input-referred
noise voltage of 0.75 nV/√Hz (at a gain of 21.3 dB). This is
achieved with a current consumption of only 27 mA per channel
(80 mW). On-chip resistor matching results in precise single-
ended gains, which are critical for accurate impedance control.
The use of a fully differential topology and negative feedback
minimizes distortion. Low second-order harmonic distortion is
particularly important in second harmonic ultrasound imaging
applications. Differential signaling enables smaller swings at each
output, further reducing third-order distortion.
Recommendation
It is highly recommended that the LG-x pins form a Kelvin type
connection to the input or probe connection ground. Simply
connecting the LG pin to ground near the device can allow
differences in potential to be amplified through the LNA. This
generally shows up as a dc offset voltage that can vary from
channel to channel and part to part given the application and
layout of the PCB (see Figure 38).
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參數(shù)描述
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AD9272BSVZ-40 功能描述:IC ADC OCT 12BIT 40MSPS 100-TQFP RoHS:是 類別:集成電路 (IC) >> 數(shù)據(jù)采集 - ADCs/DAC - 專用型 系列:- 產(chǎn)品培訓(xùn)模塊:Lead (SnPb) Finish for COTS Obsolescence Mitigation Program 標(biāo)準(zhǔn)包裝:50 系列:- 類型:數(shù)據(jù)采集系統(tǒng)（DAS） 分辨率（位）:16 b 采樣率（每秒）:21.94k 數(shù)據(jù)接口:MICROWIRE?，QSPI?，串行，SPI? 電壓電源:模擬和數(shù)字 電源電壓:1.8 V ~ 3.6 V 工作溫度:-40°C ~ 85°C 安裝類型:表面貼裝 封裝/外殼:40-WFQFN 裸露焊盤 供應(yīng)商設(shè)備封裝:40-TQFN-EP（6x6） 包裝:托盤
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