參數(shù)資料
型號: AD9211BCPZ-250
廠商: ANALOG DEVICES INC
元件分類: ADC
英文描述: 10-Bit, 170/200/250 MSPS 1.8 V A/D Converter
中文描述: 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, QCC56
封裝: 8 X 8 MM, ROHS COMPLIANT, MO-220VLLD-2, LFCSP-56
文件頁數(shù): 6/21頁
文件大?。?/td> 310K
代理商: AD9211BCPZ-250
AD9211
Preliminary Technical Data
SWITCHING SPECIFICATIONS
Table 4. (AVDD = 1.8 V, DRVDD = 1.8 V, T
MIN
= –40°C, T
MAX
= +85°C, DCS Enabled unless otherwise noted.)
AD9211-170/-200
Parameter (Conditions)
Temp
Min
Typ
Maximum Conversion Rate
1
Full
170/200
Minimum Conversion Rate
1
Full
CLK+ Pulsewidth High (t
EH
)
1
Full
TBD
CLK+ Pulsewidth Low (t
EL
)
1
Full
TBD
OUTPUT (LVDS)
Valid Time (t
V
)
Full
TBD
Propagation Delay (t
PD
)
Full
3.9
Rise Time (t
R
) (20% to 80%)
25°C
0.4
Fall Time (t
F
) (20% to 80%)
25°C
0.4
DCO Propagation Delay (t
CPD
)
Full
3.2
Data to DCO Skew (t
PD
– t
CPD
)
Full
Latency (L)
Full
5
Aperture Delay (t
A
)
25°C
TBD
Aperture Uncertainty (Jitter, t
J
)
25°C
0.2
Out of Range Recovery Time
25°C
Rev. PrA | Page 6 of 21
AD9211-250
Typ
3.9
0.4
0.4
3.2
5
TBD
0.2
Unit
MSPS
MSPS
ns
ns
ns
ns
ns
ns
ns
ns
Cycles
ns
ps rms
Cycles
Max
40
TBD
TBD
Min
250
TBD
TBD
TBD
Max
40
TBD
TBD
1
All ac specifications tested by driving CLK+ and CLK– differentially.
N–1
N
N+1
N+L
N+L+1
N+L+2
N+L+3
t
EH
t
EL
1/f
S
t
A
N–L
t
PD
L CYCLES
t
V
N-L+1
N
N+1
N+2
t
CPD
CLK+
CLK–
DATA
OUT
DCO–
DCO+
AIN
Figure 2. Timing Diagram (L=5 Cycles)
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