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參數(shù)資料
| 型號： | AD9211BCPZ-250 |
| 廠商： | ANALOG DEVICES INC |
| 元件分類： | ADC |
| 英文描述： | 10-Bit, 170/200/250 MSPS 1.8 V A/D Converter |
| 中文描述： | 1-CH 10-BIT PROPRIETARY METHOD ADC, PARALLEL ACCESS, QCC56 |
| 封裝： | 8 X 8 MM, ROHS COMPLIANT, MO-220VLLD-2, LFCSP-56 |
| 文件頁數(shù)： | 10/21頁 |
| 文件大?。?/td> | 310K |
| 代理商： | AD9211BCPZ-250 |
AD9211
Preliminary Technical Data
TERMINOLOGY
Analog Bandwidth
Rev. PrA | Page 10 of 21
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between the 50% point of the rising edge of the Clock
and the instant at which the analog input is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Crosstalk
Coupling onto one channel being driven by a low level (–40
dBFS) signal when the adjacent interfering channel is driven by
a fullscale signal.
Differential Analog Input Resistance, Differential Analog
Input Capacitance, and Differential Analog Input Impedance
The real and complex impedances measured at each analog
input port. The resistance is measured statically and the
capacitance and differential input impedances are measured
with a network analyzer.
Differential Analog Input Voltage Range
The peak-to-peak differential voltage that must be applied to
the converter to generate a full-scale response. Peak differential
voltage is computed by observing the voltage on a single pin
and subtracting the voltage from the other pin, which is 180°
out of phase. Peak-to-peak differential is computed by rotating
the input’s phase 180° and again taking the peak measurement.
The difference is then computed between both peak
measurements.
Differential Nonlinearity
The deviation of any code width from an ideal 1 LSB step.
Effective Number of Bits (ENOB)
Calculated from the measured SNR based on the equation
02
.
76
.
dB
SNR
ENOB
MEASURED
=
Clock Pulsewidth/Duty Cycle
Pulsewidth high is the minimum amount of time the ENCODE
pulse should be left in Logic 1 state to achieve rated
performance; pulsewidth low is the minimum time the Clock
pulse should be left in low state. At a given clock rate, these
specifications define an acceptable Clock duty cycle.
Full-Scale Input Power
Expressed in dBm. Computed using the following equation:
=
001
.
log
10
2
INPUT
RMS
FULLSCALE
Z
FULLSCALE
V
Power
Gain Error
The difference between the measured and ideal full-scale input
voltage range of the ADC.
Harmonic Distortion, Second
The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.
Harmonic Distortion, Third
The ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBc.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a “best straight line”
determined by a least square curve fit.
Minimum Conversion Rate
The Clock rate at which the SNR of the lowest analog signal
frequency drops by no more than 3 dB below the guaranteed
limit.
Maximum Conversion Rate
The Clock rate at which parametric testing is performed.
Output Propagation Delay
The delay between a differential crossing of CLK+ and CLK–
and the time when all output data bits are within valid logic
levels.
Noise (for Any Range within the ADC)
Calculated as follows:
×
×
=
10
10
001
.
dBFS
dBc
dBM
NOISE
V
Signal
SNR
FS
Z
where
Z
is the input impedance,
FS
is the full scale of the device
for the frequency in question,
SNR
is the value of the particular
input level, and
Signal
is the signal level within the ADC
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