參數(shù)資料
型號(hào): AD8158ACPZ
廠商: Analog Devices Inc
文件頁數(shù): 28/36頁
文件大?。?/td> 0K
描述: IC MUX/DEMUX QUAD 2X1 100LFCSP
產(chǎn)品變化通告: AD8158 Change of Default Settings 13/Aug/2009
標(biāo)準(zhǔn)包裝: 1
系列: XStream™
功能: 多路復(fù)用器/多路分解器
電路: 4 x 2:1
電壓電源: 單電源
電壓 - 電源,單路/雙路(±): 1.6 V ~ 3.6 V
電流 - 電源: 780mA
工作溫度: -40°C ~ 85°C
安裝類型: 表面貼裝
封裝/外殼: 100-VFQFN 裸露焊盤,CSP
供應(yīng)商設(shè)備封裝: 100ピンLFCSP-VQ(12x12)
包裝: 托盤
AD8158
Rev. B | Page 34 of 36
REGISTER MAP
All registers are port-level and global registers, unless otherwise noted.
Table 22. Register Definitions
Mnemonic
Addr.
Bit 7
Bit 6
Bit 5
Bit 4
Bit 3
Bit 2
Bit 1
Bit 0
Default
Reset
0x00
RESET
Switch
Control 1
0x01
LBC
LBB
LBA
SELAb/B[3]
SELAb/B[2]
SELAb/B[1]
SELAb/B[0]
0x00
Switch
Control 2
0x02
SEL4G
BICAST
0x00
Global
Squelch Ctrl
0x04
GSQLCH_ENB
0x0F
Switch Core/
Headroom
0x05
TX_HEAD
ROOM_C
TX_HEAD
ROOM_B
TX_HEAD
ROOM_A
XCORE_ENB
0x01
Mode
0x0F
MODE[1]
MODE[0]
0x00
RXA Disable
0x40
RXDIS A3
RXDIS A2
RXDIS A1
RXDIS A0
0x00
RXA Setting
0x41
AEQ[3]
AEQ[2]
AEQ[1]
AEQ[0]
0x00
RXA LOS
Control
0x51
Set to 0
LOS_FILT
Set to 0
LOS_ENB
0x05
RXA Lane 1/
RXA Lane 0
Setting
A1EQ[3]
A1EQ[2]
A1EQ[1]
A1EQ[0]
A0EQ[3]
A0EQ[2]
A0EQ[1]
A0EQ[0]
0x00
RXA Lane 3/
RXA Lane 2
Setting
A3EQ[3]
A3EQ[2]
A3EQ[1]
A3EQ[0]
A2EQ[3]
A2EQ[2]
A2EQ[1]
A2EQ[0]
0x00
RXA P/N
Swap
PNA3
PNA2
PNA1
PNA0
0x00
RXA LOS
Status
LOSA3
Sticky
LOSA2
Sticky
LOSA1
Sticky
LOSA0
Sticky
LOSA3 Active
LOSA2
Active
LOSA1
Active
LOSA0
Active
TXA Disable
0x48
TXDIS A3
TXDIS A2
TXDIS A1
TXDIS A0
0x00
TXA Level/PE
Control
0x49
ALEV[1]
ALEV[0]
APE[2]
APE[1]
APE[0]
0x20
TXA Lane1/
TXA Lane 0
PE Setting
A1PE[2]
A1PE[1]
A1PE[0]
A0PE[2]
A0PE[1]
A0PE[0]
0x00
TXA Lane2/3
PE Setting
A3PE[2]
A3PE[1]
A3PE[0]
A2PE[2]
A2PE[1]
A2PE[0]
0x00
TXA Per-Lane
Level Setting
A3OLEV[1]
A3OLEV[0]
A2OLEV[1]
A2OLEV[0]
A1OLEV[1]
A1OLEV[0]
A0OLEV[1]
A0OLEV[0]
0xAA
RXB Disable
0x80
RXDIS B3
RXDIS B2
RXDIS B1
RXDIS B0
0x00
RXB Setting
0x81
BEQ[3]
BEQ[2]
BEQ[1]
BEQ[0]
0x00
RXB LOS Ctrl
0x91
Set to 0
LOS_FILT
Set to 0
LOS_ENB
0x05
RXB Lane 1/
RXB Lane 0
Setting
B1EQ[3]
B1EQ[2]
B1EQ[1]
B1EQ[0]
B0EQ[3]
B0EQ[2]
B0EQ[1]
B0EQ[0]
0x00
RXB Lane 3/
RXB Lane 2
Setting
B3EQ[3]
B3EQ[2]
B3EQ[1]
B3EQ[0]
B2EQ[3]
B2EQ[2]
B2EQ[1]
B2EQ[0]
0x00
RXB P/N
Swap
PNB3
PNB2
PNB1
PNB0
0x00
RXB LOS
Status
LOSB3
Sticky
LOSB2
Sticky
LOSB1
Sticky
LOSB0
Sticky
LOSB3 Active
LOSB2
Active
LOSB1
Active
LOSB0
Active
TXB Disable
0x88
TXDIS B3
TXDIS B2
TXDIS B1
TXDIS B0
0x00
TXB Level/PE
Control
0x89
BLEV[1]
BLEV[0]
BPE[2]
BPE[1]
BPE[0]
0x20
TXB Lane1/
TXB Lane 0
PE Setting
B1PE[2]
B1PE[1]
B1PE[0]
B0PE[2]
B0PE[1]
B0PE[0]
0x00
TXB Lane2/
TXB Lane 3
PE Setting
B3PE[2]
B3PE[1]
B3PE[0]
B2PE[2]
B2PE[1]
B2PE[0]
0x00
TXB Per-Lane
Level Setting
B3OLEV[1]
B3OLEV[0]
B2OLEV[1]
B2OLEV[0]
B1OLEV[1]
B1OLEV[0]
B0OLEV[1]
B0OLEV[0]
0xAA
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