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| 型號： | AD8158ACPZ |
| 廠商： | Analog Devices Inc |
| 文件頁數(shù)： | 18/36頁 |
| 文件大?。?/td> | 0K |
| 描述： | IC MUX/DEMUX QUAD 2X1 100LFCSP |
| 產(chǎn)品變化通告： | AD8158 Change of Default Settings 13/Aug/2009 |
| 標準包裝： | 1 |
| 系列： | XStream™ |
| 功能： | 多路復用器/多路分解器 |
| 電路： | 4 x 2:1 |
| 電壓電源： | 單電源 |
| 電壓 - 電源，單路/雙路(±)： | 1.6 V ~ 3.6 V |
| 電流 - 電源： | 780mA |
| 工作溫度： | -40°C ~ 85°C |
| 安裝類型： | 表面貼裝 |
| 封裝/外殼： | 100-VFQFN 裸露焊盤，CSP |
| 供應商設備封裝： | 100ピンLFCSP-VQ（12x12） |
| 包裝： | 托盤 |
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AD8158
Rev. B | Page 25 of 36
I2C CONTROL INTERFACE
SERIAL INTERFACE GENERAL FUNCTIONALITY
The AD8158 register set is controlled through a 2-wire I2C
interface. The AD8158 acts only as an I2C slave device. The
7-bit slave address for the AD8158 I2C interface contains the
static value b1010 for the upper four bits. The lower three bits
are controlled by the input pins, I2C_A[2:0].
Therefore, the I2C bus in the system must include an I2C master
to configure the AD8158 and other I2C devices that may be on
the bus. Data transfers are controlled through the use of the two
I2C wires: the SCL input clock pin and the SDA bidirectional
data pin.
The AD8158 I2C interface can be run in the standard (100 kHz)
and fast (400 kHz) modes. The SDA line changes value only
when the SCL pin is low, with two exceptions. To indicate the
beginning or continuation of a transfer, the SDA pin is driven
low while the SCL pin is high, and to indicate the end of a
transfer, the SDA line is driven high while the SCL line is high.
Therefore, it is important to control the SCL clock to toggle
only when the SDA line is stable unless indicating a start,
repeated start, or stop condition.
I2C INTERFACE DATA TRANSFERS: DATA WRITE
To write data to the AD8158 register set, a microcontroller or
any other I2C master must send the appropriate control signals
to the AD8158 slave device. The following steps must be taken,
where the signals are controlled by the I2C master, unless other-
wise specified. For a diagram of the procedure, see Figure 41.
1.
Send a start condition (while holding the SCL line high,
pull the SDA line low).
2.
Send the AD8158 part address (seven bits) whose upper
four bits are the static value b1010 and whose lower three
bits are controlled by the I2C_A[2:0] input pins. This
transfer should be MSB first.
3.
Send the write indicator bit (0).
4.
Wait for the AD8158 to acknowledge the request.
5.
Send the register address (eight bits) to which data is to be
written. This transfer should be MSB first.
6.
Wait for the AD8158 to acknowledge the request.
7.
Send the data (eight bits) to be written to the register whose
address was set in Step 5. This transfer should be MSB first.
8.
Wait for the AD8158 to acknowledge the request.
9.
Do one or more of the following:
a.
Send a stop condition (while holding the SCL line
high, pull the SDA line high) and release control of
the bus.
b.
Send a repeated start condition (while holding the
SCL line high, pull the SDA line low) and continue
with Step 2 in this procedure to perform another write.
c.
Send a repeated start condition (while holding the
SCL line high, pull the SDA line low) and continue
with Step 2 of the read procedure (in the I2C Interface
Data Transfers: Data Read section) to perform a read
from another address.
d.
Send a repeated start condition (while holding the
SCL line high, pull the SDA line low) and continue
with Step 8 of the read procedure (in the I2C Interface
Data Transfers: Data Read section) to perform a read
from the same address set in Step 5.
In Figure 41, the AD8158 write process is shown. The SCL
signal is shown along with a general write operation and a
specific example. In this example, the value 0x92 is written to
Address 0x6D of an AD8158 device with a part address of 0x53.
The part address is seven bits wide and is composed of the
AD8158 static upper four bits (b1010) and the pin-programmable
lower three bits (I2C_A[2:0]). The address pins are set to b011.
In Figure 41, the corresponding step number is visible in the
circle under the waveform. The SCL line is driven by the I2C
master and never by the AD8158 slave. As for the SDA line, the
data in the shaded polygons is driven by the AD8158, whereas
the data in the nonshaded polygons is driven by the I2C master.
The end phase case shown is that of Step 9a.
It is important to note that the SDA line changes only when the
SCL line is low, except for the case of sending a start, stop, or
repeated start condition (Step 1 and Step 9 in this case).
START
R/W ACK
ACK
STOP
DATA
ADDR
[2:0]
b1010
REGISTER ADDR
SCL
SDA
1
2
3
4
5
6
7
8
9a
06
64
6-
1
42
Figure 41. I2C Write Diagram
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相關代理商/技術參數(shù) |
參數(shù)描述 |
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| AD8158-EVALZ | 制造商:Analog Devices 功能描述:EVALUATION BOARD - Bulk |
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| AD8159 | 制造商:AD 制造商全稱:Analog Devices 功能描述:3.2 Gbps Quad Buffer Mux/Demux |
| AD8159ASVZ | 功能描述:IC MUX/DEMUX QUAD BUFF 100TQFP RoHS:是 類別:集成電路 (IC) >> 接口 - 專用 系列:XStream™ 特色產(chǎn)品:NXP - I2C Interface 標準包裝:1 系列:- 應用:2 通道 I²C 多路復用器 接口:I²C，SM 總線 電源電壓:2.3 V ~ 5.5 V 封裝/外殼:16-TSSOP（0.173"，4.40mm 寬） 供應商設備封裝:16-TSSOP 包裝:剪切帶 (CT) 安裝類型:表面貼裝 產(chǎn)品目錄頁面:825 (CN2011-ZH PDF) 其它名稱:568-1854-1 |
| AD8159-EVAL-AC | 制造商:Analog Devices 功能描述:EVAL KIT FOR AC-COUPLED EVAL BD - Bulk |
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